On Thu, 29 Mar 2012 02:26:36 +0800, Daniel Kurtz <djkurtz@xxxxxxxxxxxx> wrote: > The i915 is only able to generate a STOP cycle (i.e. finalize an i2c > transaction) during a DATA or WAIT phase. In other words, the > controller rejects a STOP requested as part of the first transaction in a > sequence. The original docs have "this can only cause a STOP to be generated if a GMBUS cycle is generated, the GMBUS is currently in a data phase, or it is in a WAIT phase." So from that it seems STOP | INDEX? | WAIT is always a valid combination and is explicitly listed in the register set. I defer to actual testing though ;) -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
