TCON dotclock compute the desired DCLK register divider based on panel pixel clock along with input DCLK or DSI clock dividers from tcon driver. The current code allowing an input DCLK dividers ranging from 4 to 127, but the existing dclock logic is unable to compute the desired output DCLK divider value for new panels instead it ended-up producing unknown divider values which no longer exists. So, add the computation logic 'format/lanes' to dclk min and max dividers and indeed it produced the desired DCLK divider even for the new panels. This computation logic align with Allwinner A64 BSP, hoping that would work even for A33. Tested this on 3 different panels, and below are the desired divider values with respect to pixel clock frequency. - 55MHz pixel clock with 4-lane panel, and the desired DSI clock divider is 6 with the output parent clock rate of 330MHz. - 30MHz pixel clock with 4-lane panel, and the desired DSI clock divider is 6 with parent clock rate of 180MHz. - 27.5Mhz pixel clock with 2-lane pane, and the desired DSI clock divider is 12 with the output parent clock rate of 330MHz. Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> Tested-by: Merlijn Wajer <merlijn@xxxxxxxxxx> --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 3da75a0c5c5d..4d5a158d9a25 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -342,8 +342,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; - tcon->dclk_min_div = 4; - tcon->dclk_max_div = 127; + tcon->dclk_min_div = bpp / lanes; + tcon->dclk_max_div = bpp / lanes; sun4i_tcon0_mode_set_common(tcon, mode); -- 2.18.0.321.gffc6fa0e3 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
