On Wed, Mar 28, 2012 at 03:30:13PM +0100, Chris Wilson wrote: > On Wed, 28 Mar 2012 21:21:42 +0800, Daniel Kurtz <djkurtz@xxxxxxxxxxxx> wrote: > > On Wed, Mar 28, 2012 at 9:05 PM, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > > > We do need the write flush here (and set_data) as the next action is a > > > udelay loop which is not per-se a mb. > > > > Now I am confused. I915_WRITE_NOTRACE() calls writel(), which has an > > explicit mb(); Why do you need another mb? > > Nominally writel isn't a memory barrier. I see that x86 does include mb > in its writel define. However, if memory serves, that is only a write > barrier to memory (equivalent of mfence), and not a PCI write flush/barrier > for which we need to an explicit PCI read. Yeah, I think for gmbus here we should only drop the POSTING_READ if we'll read a register right afterwards anyway. Let's better be slightly paranoid about this. -Daniel -- Daniel Vetter Mail: daniel@xxxxxxxx Mobile: +41 (0)79 365 57 48 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
