On Fri, Jan 25, 2019 at 01:28:52AM +0530, Jagan Teki wrote: > The MIPI DSI controller in Allwinner A64 is similar to A33. > > But unlike A33, A64 doesn't have DSI_SCLK gating which eventually > set the mod clock rate for the controller. > > So, use the DSI_DPHY gating for the similar purpose of mod clock > so-that the controller can operate properly. > > Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt > index 69e233e8fad1..dbda2e567760 100644 > --- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt > +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt > @@ -12,6 +12,7 @@ The DSI Encoder generates the DSI signal from the TCON's. > Required properties: > - compatible: value must be one of: > * allwinner,sun6i-a31-mipi-dsi > + * "allwinner,sun50i-a64-mipi-dsi", "allwinner,sun6i-a31-mipi-dsi" The other line doesn't have quotes, we should be consistent Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
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