On Wed, Jan 23, 2019 at 04:41:44PM +0300, Dmitry Osipenko wrote:
> 23.01.2019 12:39, Thierry Reding пишет:
> > From: Thierry Reding <treding@xxxxxxxxxx>
> >
> > On Tegra186 and later, the ARM SMMU provides an input address space that
> > is 48 bits wide. However, memory clients can only address up to 40 bits.
> > If the geometry is used as-is, allocations of IOVA space can end up in a
> > region that cannot be addressed by the memory clients.
> >
> > To fix this, restrict the IOVA space to the DMA mask of the host1x
> > device. Note that, technically, the IOVA space needs to be restricted to
> > the intersection of the DMA masks for all clients that are attached to
> > the IOMMU domain. In practice using the DMA mask of the host1x device is
> > sufficient because all host1x clients share the same DMA mask.
> >
> > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> > ---
> > drivers/gpu/drm/tegra/drm.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
> > index 271c7a5fc954..0c5f1e6a0446 100644
> > --- a/drivers/gpu/drm/tegra/drm.c
> > +++ b/drivers/gpu/drm/tegra/drm.c
> > @@ -136,11 +136,12 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
> >
> > if (tegra->domain) {
> > u64 carveout_start, carveout_end, gem_start, gem_end;
> > + u64 dma_mask = dma_get_mask(&device->dev);
> > dma_addr_t start, end;
> > unsigned long order;
> >
> > - start = tegra->domain->geometry.aperture_start;
> > - end = tegra->domain->geometry.aperture_end;
> > + start = tegra->domain->geometry.aperture_start & dma_mask;
> > + end = tegra->domain->geometry.aperture_end & dma_mask;
> >
> > gem_start = start;
> > gem_end = end - CARVEOUT_SZ;
> >
>
> Wow, so IOVA could address >32bits on later Tegra's. AFAIK, currently
> there is no support for a proper programming of the 64bit addresses in
> the drivers code, hence.. won't it make sense to force IOVA mask to
> 32bit for now and hope that the second halve of address registers
> happen to be 0x00000000 in HW?
Actually we do have proper programming for 40 bit addresses in the
display driver code for Tegra186 and later, see:
drivers/gpu/drm/tegra/hub.c:
tegra_shared_plane_atomic_update()
Code to support that on Tegra210 and earlier should be almost identical.
I'll try to add that as well. It's not actually necessary there because
with an SMMU enabled on those chips, the address space will be 32 bits.
I suspect that there could be an issue with running without an SMMU on
Tegra124 (with > 2 GiB of memory and LPAE enabled) or Tegra210. I'll see
if I can produce a case where this actually fails and then add the code
for proper programming there.
In the meantime, I've sent out a v2 of the series that takes care of
properly programming the various bits in host1x required for full 40-bit
addresses on Tegra186 and later.
Thierry
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