Hi Robert,
On Thu, Jan 10, 2019 at 6:34 AM Robert Chiras <robert.chiras@xxxxxxx> wrote:
>
> The eLCDIF controller has control pin for the external LCD reset pin.
> Add support for it and assert this pin in enable and de-assert it in
> disable.
> Also, correct the pm_runtime_enable call, since it was made too early in
> the probe, causing issues to DRM enable routines.
The pm_runtime change should be on a different patch.
> Signed-off-by: Robert Chiras <robert.chiras@xxxxxxx>
> ---
> drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 ++++++++++--
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 20 ++++++++------------
> drivers/gpu/drm/mxsfb/mxsfb_regs.h | 1 +
> 3 files changed, 19 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> index b62b607..8d1b6a6 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> @@ -230,9 +230,12 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
> clk_prepare_enable(mxsfb->clk_disp_axi);
> clk_prepare_enable(mxsfb->clk);
>
> - if (mxsfb->devdata->ipversion >= 4)
> + if (mxsfb->devdata->ipversion >= 4) {
> writel(CTRL2_OUTSTANDING_REQS(REQ_16),
> mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
> + /* Assert LCD Reset bit */
> + writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
> + }
>
> /* If it was disabled, re-enable the mode again */
> writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
> @@ -250,9 +253,12 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
> {
> u32 reg;
>
> - if (mxsfb->devdata->ipversion >= 4)
> + if (mxsfb->devdata->ipversion >= 4) {
> writel(CTRL2_OUTSTANDING_REQS(0x7),
> mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
> + /* De-assert LCD Reset bit */
> + writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
> + }
>
> writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);
>
> @@ -346,6 +352,8 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
> return;
>
> clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
> + DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n",
> + m->crtc_clock, (int)(clk_get_rate(mxsfb->clk) / 1000));
This unrelated change should also be in a different patch.
>
> DRM_DEV_DEBUG_DRIVER(drm->dev,
> "Connector bus_flags: 0x%08X\n", bus_flags);
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> index f528a37..135b8e1 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> @@ -287,7 +287,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
> if (IS_ERR(mxsfb->base))
> return PTR_ERR(mxsfb->base);
>
> - mxsfb->clk = devm_clk_get(drm->dev, NULL);
> + mxsfb->clk = devm_clk_get(drm->dev, "pix");
This breaks mx23 and mx28 as there is no "pix" clock defined in their
dtsi files.
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