tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head: d2d07f246b126b23d02af0603b83866a3c3e2483
commit: fdc916c8be24375d63c36ae363f71e59becfb8f2 [262/270] drm/amdgpu: Add sysfs file for PCIe usage v4
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 8.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout fdc916c8be24375d63c36ae363f71e59becfb8f2
# save the attached .config to linux build tree
GCC_VERSION=8.1.0 make.cross ARCH=ia64
Note: the radeon-alex/amd-staging-drm-next HEAD d2d07f246b126b23d02af0603b83866a3c3e2483 builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/amd/amdgpu/si.c:28:
drivers/gpu/drm/amd/amdgpu/si.c: In function 'si_get_pcie_usage':
>> drivers/gpu/drm/amd/amdgpu/si.c:1341:35: error: 'PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK' undeclared (first use in this function); did you mean 'PCI_PM_CTRL_DATA_SEL_MASK'?
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1010:36: note: in definition of macro 'REG_FIELD_MASK'
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1341:12: note: in expansion of macro 'REG_SET_FIELD'
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/si.c:1341:35: note: each undeclared identifier is reported only once for each function it appears in
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1010:36: note: in definition of macro 'REG_FIELD_MASK'
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1341:12: note: in expansion of macro 'REG_SET_FIELD'
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
^~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/si.c:1341:35: error: 'PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT' undeclared (first use in this function); did you mean 'ixPCIE_PERF_CNTL_EVENT0_PORT_SEL'?
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1009:37: note: in definition of macro 'REG_FIELD_SHIFT'
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1341:12: note: in expansion of macro 'REG_SET_FIELD'
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
^~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/si.c:1342:35: error: 'PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK' undeclared (first use in this function); did you mean 'PCI_PM_CTRL_DATA_SEL_MASK'?
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1010:36: note: in definition of macro 'REG_FIELD_MASK'
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1342:12: note: in expansion of macro 'REG_SET_FIELD'
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
^~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/si.c:1342:35: error: 'PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT' undeclared (first use in this function); did you mean 'ixPCIE_PERF_CNTL_EVENT1_PORT_SEL'?
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1009:37: note: in definition of macro 'REG_FIELD_SHIFT'
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1342:12: note: in expansion of macro 'REG_SET_FIELD'
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/si.c:1364:31: error: 'PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK' undeclared (first use in this function)
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1010:36: note: in definition of macro 'REG_FIELD_MASK'
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1364:12: note: in expansion of macro 'REG_GET_FIELD'
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/si.c:1364:31: error: 'PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT' undeclared (first use in this function)
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1009:37: note: in definition of macro 'REG_FIELD_SHIFT'
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1364:12: note: in expansion of macro 'REG_GET_FIELD'
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/si.c:1365:31: error: 'PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK' undeclared (first use in this function)
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1010:36: note: in definition of macro 'REG_FIELD_MASK'
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1365:12: note: in expansion of macro 'REG_GET_FIELD'
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/si.c:1365:31: error: 'PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT' undeclared (first use in this function)
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1009:37: note: in definition of macro 'REG_FIELD_SHIFT'
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
^~~
drivers/gpu/drm/amd/amdgpu/si.c:1365:12: note: in expansion of macro 'REG_GET_FIELD'
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
^~~~~~~~~~~~~
vim +1341 drivers/gpu/drm/amd/amdgpu/si.c
1325
1326 static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1327 uint64_t *count1)
1328 {
1329 uint32_t perfctr = 0;
1330 uint64_t cnt0_of, cnt1_of;
1331 int tmp;
1332
1333 /* This reports 0 on APUs, so return to avoid writing/reading registers
1334 * that may or may not be different from their GPU counterparts
1335 */
1336 if (adev->flags & AMD_IS_APU)
1337 return;
1338
1339 /* Set the 2 events that we wish to watch, defined above */
1340 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
> 1341 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
> 1342 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1343
1344 /* Write to enable desired perf counters */
1345 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1346 /* Zero out and enable the perf counters
1347 * Write 0x5:
1348 * Bit 0 = Start all counters(1)
1349 * Bit 2 = Global counter reset enable(1)
1350 */
1351 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1352
1353 msleep(1000);
1354
1355 /* Load the shadow and disable the perf counters
1356 * Write 0x2:
1357 * Bit 0 = Stop counters(0)
1358 * Bit 1 = Load the shadow counters(1)
1359 */
1360 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1361
1362 /* Read register values to get any >32bit overflow */
1363 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1364 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1365 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1366
1367 /* Get the values and add the overflow */
1368 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1369 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1370 }
1371
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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