Hi Giulio, On Thu, 6 Dec 2018 at 22:00, Giulio Benetti <giulio.benetti@xxxxxxxxxxxxxxxx> wrote: > > Hi Jonathan, > > Il 06/12/2018 08:29, Jonathan Liu ha scritto: > > Hi Giulio, > > > > On Thu, 15 Feb 2018 at 17:54, Giulio Benetti > > <giulio.benetti@xxxxxxxxxxxxxxxx> wrote: > >> > >> Differently from other Lcd signals, HSYNC and VSYNC signals > >> result inverted if their bits are cleared to 0. > >> > >> Invert their settings of IO_POL register. > >> > >> Signed-off-by: Giulio Benetti <giulio.benetti@xxxxxxxxxxxxxxxx> > >> --- > >> drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- > >> 1 file changed, 2 insertions(+), 2 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c > >> index 3c15cf2..aaf911a 100644 > >> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > >> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > >> @@ -389,10 +389,10 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, > >> SUN4I_TCON0_BASIC3_H_SYNC(hsync)); > >> > >> /* Setup the polarity of the various signals */ > >> - if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) > >> + if (mode->flags & DRM_MODE_FLAG_PHSYNC) > >> val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; > >> > >> - if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) > >> + if (mode->flags & DRM_MODE_FLAG_PVSYNC) > >> val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; > >> > >> regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, > > > > I am running Linux 4.19.6 and noticed with Olimex LCD-OLinuXino-7TS 7" > > LCD touchscreen (Innolux AT070TN92) connected to Olimex > > A20-OLinuXino-MICRO that the image does not display correctly after > > this change. > > The image is shifted to the right. > > > > Reverting the change results in the image being displayed correctly on > > the screen. > > > > I have in the device tree a "panel" node with compatible = > > "innolux,at070tn92" which uses the timings in > > drivers/gpu/drm/panel/panel-simple.c. > > > > Any ideas? > > Checking Display Datasheet: > https://www.olimex.com/Products/Retired/A13-LCD7-TS/resources/S700-AT070TN92.pdf > > Page 13 section 3.3.2 you can see it needs active low VS and HS. > > You can refer to this Thread and check scope captures about VS and HS > versus TCON0_IOPOL register: > https://lists.freedesktop.org/archives/dri-devel/2018-January/163874.html > > There should be something that wrongly sets one of these or both: > mode->flags |= DRM_MODE_FLAG_PHSYNC; > and/or > mode->flags |= DRM_MODE_FLAG_PVSYNC; > > Checked in panel-simple.c but it's not there. flags is 0 because it is not assigned in the struct definition for the panel. Before this change, TCON0_IO_POL_REG would be 0x03000000 (both bits set to 1) and image displays correctly. After this change, TCON0_IO_POL_REG is 0x00000000 (both bits set to 0) and image doesn't display correctly. Checked using "devmem2 0x01c0c088" on A20-OLinuXino-MICRO Rev J. > > At the moment I don't have a board to check it with me, I'll try to do > it soon, but I'm full with other work at the moment. > > If you have the chance to debug you could try to find in which point > mode->flags gets changed with those 2 flags. > > When the problem came out I've noticed the same thing for u-boot too but > it's been decided to not patch it because in that case every single > sunxi defconfig had to be changed from: > CONFIG_VIDEO_LCD_MODE="...,sync:3,..." > to: > CONFIG_VIDEO_LCD_MODE="...,sync:0,..." > and it would have been a great mess, probably not worth it: > https://lists.denx.de/pipermail/u-boot/2018-February/321405.html > > So keep in mind that TCON driver works differently for HS and > VS(inverted) polarity in u-boot and linux. > > Hope to work this out soon. Regards, Jonathan _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
