My local changes for VOP and HDMI. (PART 2)
From 81bc4d4f83b57161c8ba7005875a2f9ff9ec1d3a Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@xxxxxxxxxxxxxx>
Date: Mon, 6 Nov 2017 11:50:54 +0800
Subject: [PATCH] clk: rockchip: rk3188: Add CLK_SET_RATE_PARENT for lcdc dclk
Add CLK_SET_RATE_PARENT for lcdc dclk.
Signed-off-by: Finley Xiao <finley.xiao@xxxxxxxxxxxxxx>
Signed-off-by: Johan Jonker <jbx9999@xxxxxxxxxxx>
---
drivers/clk/rockchip/clk-rk3188.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 7ea20341e..5ecf28854 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -586,12 +586,12 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 1, GFLAGS),
- MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,
+ MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
- MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,
+ MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
--
2.11.0
From c5cee17f7396f0539ddf6ffe9e2da2fc14270dc1 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@xxxxxxxxxxxxxx>
Date: Fri, 16 Nov 2018 16:42:27 +0100
Subject: [PATCH] clk: rockchip: rk3188: make hclk_ahb2apb critical
Make hclk_ahb2apb critical.
Signed-off-by: Finley Xiao <finley.xiao@xxxxxxxxxxxxxx>
Signed-off-by: Johan Jonker <jbx9999@xxxxxxxxxxx>
---
drivers/clk/rockchip/clk-rk3188.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 5ecf28854..71a8dfd22 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -759,6 +759,7 @@ static const char *const rk3188_critical_clocks[] __initconst = {
"pclk_peri",
"hclk_cpubus",
"hclk_vio_bus",
+ "hclk_ahb2apb",
};
static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
--
2.11.0
From b5d264cbd211cc92751c8d7e214229ae2b674ec8 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@xxxxxxxxxxxxxx>
Date: Wed, 6 Dec 2017 17:53:00 +0800
Subject: [PATCH] clk: rockchip: rk3188: Rename i2s hclk id
Rename i2s hclk id.
Signed-off-by: Finley Xiao <finley.xiao@xxxxxxxxxxxxxx>
Signed-off-by: Johan Jonker <jbx9999@xxxxxxxxxxx>
---
arch/arm/boot/dts/rk3066a.dtsi | 6 +++---
arch/arm/boot/dts/rk3188.dtsi | 2 +-
drivers/clk/rockchip/clk-rk3188.c | 6 +++---
include/dt-bindings/clock/rk3188-cru-common.h | 6 +++---
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 112d2bf8e..ec31f9aff 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -68,7 +68,7 @@
dmas = <&dmac1_s 4>, <&dmac1_s 5>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+ clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <8>;
rockchip,capture-channels = <2>;
status = "disabled";
@@ -85,7 +85,7 @@
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
+ clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S1>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "disabled";
@@ -102,7 +102,7 @@
dmas = <&dmac1_s 9>, <&dmac1_s 10>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
+ clocks = <&cru HCLK_I2S1_2CH>, <&cru SCLK_I2S2>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 7e0dc5263..9d0b12ec1 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -136,7 +136,7 @@
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+ clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "disabled";
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 71a8dfd22..404f2ae05 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -457,7 +457,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
/* hclk_cpu gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
- GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
+ GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
/* hclk_ahb2apb is part of a clk branch */
@@ -642,8 +642,8 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(0), 12, GFLAGS,
&rk3066a_i2s2_fracmux),
- GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
- GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
+ GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
index dc2101a63..1329c993e 100644
--- a/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -120,9 +120,9 @@
#define HCLK_OTG0 451
#define HCLK_EMAC 452
#define HCLK_SPDIF 453
-#define HCLK_I2S0 454
-#define HCLK_I2S1 455
-#define HCLK_I2S2 456
+#define HCLK_I2S0_2CH 454
+#define HCLK_I2S1_2CH 455
+#define HCLK_I2S_8CH 456
#define HCLK_OTG1 457
#define HCLK_HSIC 458
#define HCLK_HSADC 459
--
2.11.0
From 1c0923ef9260c9074b0c02df60c733c8319d9b40 Mon Sep 17 00:00:00 2001
From: Zheng Yang <zhengyang@xxxxxxxxxxxxxx>
Date: Tue, 27 Nov 2018 17:57:39 +0100
Subject: [PATCH] ARM: dts: rockchip: add rk3066 hdmi nodes
This patch adds the hdmi nodes to rk3066.
Signed-off-by: Zheng Yang <zhengyang@xxxxxxxxxxxxxx>
Signed-off-by: Johan Jonker <jbx9999@xxxxxxxxxxx>
---
arch/arm/boot/dts/rk3066a.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 29e835bd7..0d9be2d3d 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -79,6 +79,10 @@
vop0_out: port {
#address-cells = <1>;
#size-cells = <0>;
+ vop0_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in_vop0>;
+ };
};
};
@@ -102,6 +106,27 @@
};
};
+ hdmi: hdmi@10116000 {
+ compatible = "rockchip,rk3066-hdmi";
+ reg = <0x10116000 0x2000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HDMI>;
+ clock-names = "hclk";
+ rockchip,grf = <&grf>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
+ status = "disabled";
+
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in_vop0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vop0_out_hdmi>;
+ };
+ };
+ };
+
i2s0: i2s@10118000 {
compatible = "rockchip,rk3066-i2s";
reg = <0x10118000 0x2000>;
@@ -116,6 +141,7 @@
clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <8>;
rockchip,capture-channels = <2>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -133,6 +159,7 @@
clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S1>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -150,6 +177,7 @@
clocks = <&cru HCLK_I2S1_2CH>, <&cru SCLK_I2S2>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -410,6 +438,16 @@
};
};
+ hdmi {
+ hdmi_hpd: hdmi-hpd {
+ rockchip,pins = <RK_GPIO0 0 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ hdmii2c_xfer: hdmii2c-xfer {
+ rockchip,pins = <RK_GPIO0 1 RK_FUNC_1 &pcfg_pull_none>,
+ <RK_GPIO0 2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
pwm0 {
pwm0_out: pwm0-out {
rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
--
2.11.0
From 2b570860410fdde1f01a019734798ba2a9fd5633 Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx9999@xxxxxxxxxxx>
Date: Tue, 27 Nov 2018 19:26:39 +0100
Subject: [PATCH] ARM: dts: rockchip: rk3066a-mk808: enable vop0 node
This patch enables the vop0 node for a MK808 with rk3066a processor.
Signed-off-by: Johan Jonker <jbx9999@xxxxxxxxxxx>
---
arch/arm/boot/dts/rk3066a-mk808.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index b6a8a82d2..10e1c5567 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -151,6 +151,10 @@
status = "okay";
};
+&vop0 {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
--
2.11.0
From f76df32018cf1963d3c11e1d366cd6fa77cea9f9 Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx9999@xxxxxxxxxxx>
Date: Tue, 20 Nov 2018 18:17:04 +0100
Subject: [PATCH] ARM: dts: rockchip: rk3066a-mk808: enable hdmi nodes
This patch enables the hdmi nodes for a MK808 with rk3066a processor.
Signed-off-by: Johan Jonker <jbx9999@xxxxxxxxxxx>
---
arch/arm/boot/dts/rk3066a-mk808.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index 10e1c5567..a9f2f183c 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -91,6 +91,14 @@
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_in_vop0 {
+ status = "okay";
+};
+
&mmc0 {
bus-width = <4>;
cap-mmc-highspeed;
--
2.11.0
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