>-----Original Message----- >From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of >Manasi Navare >Sent: Tuesday, November 20, 2018 10:37 AM >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; dri-devel@xxxxxxxxxxxxxxxxxxxxx >Subject: [Intel-gfx] [PATCH v10 01/23] drm/dsc: Modify DRM helper to return >complete DSC color depth capabilities > >DSC DPCD color depth register advertises its color depth capabilities by setting >each of the bits that corresponding to a specific color depth. This patch defines >those specific color depths and adds a helper to return an array of color depth >capabilities. > >v2: >* Simplify the logic (Ville) > >Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx> >Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> Implementation looks good. It is used properly in the atomic check patch too... Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> >--- > drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++------ > include/drm/drm_dp_helper.h | 3 ++- > 2 files changed, 10 insertions(+), 7 deletions(-) > >diff --git a/drivers/gpu/drm/drm_dp_helper.c >b/drivers/gpu/drm/drm_dp_helper.c index 6d483487f2b4..2d6c491a0542 100644 >--- a/drivers/gpu/drm/drm_dp_helper.c >+++ b/drivers/gpu/drm/drm_dp_helper.c >@@ -1428,17 +1428,19 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8 >dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) > } > EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); > >-u8 drm_dp_dsc_sink_max_color_depth(const u8 >dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) >+int drm_dp_dsc_sink_supported_input_bpcs(const u8 >dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], >+ u8 dsc_bpc[3]) > { >+ int num_bpc = 0; > u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - >DP_DSC_SUPPORT]; > > if (color_depth & DP_DSC_12_BPC) >- return 12; >+ dsc_bpc[num_bpc++] = 12; > if (color_depth & DP_DSC_10_BPC) >- return 10; >+ dsc_bpc[num_bpc++] = 10; > if (color_depth & DP_DSC_8_BPC) >- return 8; >+ dsc_bpc[num_bpc++] = 8; > >- return 0; >+ return num_bpc; > } >-EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth); >+EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index >3314e91f6eb3..5736c942c85b 100644 >--- a/include/drm/drm_dp_helper.h >+++ b/include/drm/drm_dp_helper.h >@@ -1123,7 +1123,8 @@ drm_dp_is_branch(const u8 >dpcd[DP_RECEIVER_CAP_SIZE]) > u8 drm_dp_dsc_sink_max_slice_count(const u8 >dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], > bool is_edp); > u8 drm_dp_dsc_sink_line_buf_depth(const u8 >dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); >-u8 drm_dp_dsc_sink_max_color_depth(const u8 >dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]); >+int drm_dp_dsc_sink_supported_input_bpcs(const u8 >dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], >+ u8 dsc_bpc[3]); > > static inline bool > drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) >-- >2.19.1 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
