A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.
v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: Imre Deak <imre.deak@xxxxxxxxx>
Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_ddi.c | 6 ++++++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c | 25 +++++++++++++++++++++++++
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 044203504a3d..aeb454c3573c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2154,6 +2154,12 @@ static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
+ /*
+ * VDSC power is needed when DSC is enabled
+ */
+ if (crtc_state->dsc_params.compression_enable)
+ domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return domains;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5b53fc262b91..92e987fc3d9f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1857,6 +1857,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index a13b776dc8fa..17ef78652f71 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -578,6 +578,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ /*
+ * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+ * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+ * For any other transcoder, VDSC/joining uses the power well associated
+ * with the pipe/transcoder in use. Hence another reference on the
+ * transcoder power domain will suffice.
+ */
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else
+ return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1008,6 +1026,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
if (!crtc_state->dsc_params.compression_enable)
return;
+ /* Enable Power wells for VDSC/joining */
+ intel_display_power_get(dev_priv,
+ intel_dsc_power_domain(crtc_state));
+
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1060,4 +1082,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
RIGHT_BRANCH_VDSC_ENABLE);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+ /* Disable Power wells for VDSC/joining */
+ intel_display_power_put(dev_priv,
+ intel_dsc_power_domain(old_crtc_state));
}
--
2.19.1
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