Comment # 15
on bug 108625
from Carsten Haitzler
And lo and behold:
--- ./include/drm/drm_cache.h~ 2018-08-12 21:41:04.000000000 +0100
+++ ./include/drm/drm_cache.h 2018-11-16 11:06:16.976842816 +0000
@@ -48,7 +48,7 @@
#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
return false;
#else
- return true;
+ return false;
#endif
}
Makes it work. Of course this isn't a brilliant patch, but indeed there is
something up with the way write combined memory is handled on ARM here. but
disabling WC for all ARM DRM devices might be too much of a sledgehammer... I'm
going to look into a less sledge-hammer solution that might make this work more
universally. I'll get back to you on that.
You are receiving this mail because:
- You are the assignee for the bug.
_______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
