On 29.10.2018 12:46, Tomi Valkeinen wrote:
> Initially DP0_SRCCTRL is set to a static value which includes
> DP0_SRCCTRL_LANES_2 and DP0_SRCCTRL_BW27, even when only 1 lane of
> 1.62Gbps speed is used. DP1_SRCCTRL is configured to a magic number.
>
> This patch changes the configuration as follows:
>
> Configure DP0_SRCCTRL by using tc_srcctrl() which provides the correct
> value.
>
> DP1_SRCCTRL needs to bits to be set to the same value as DP0_SRCCTRL:
s/to/two/
> SSCG and BW27. All other bits can be zero.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
> ---
> drivers/gpu/drm/bridge/tc358767.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index fee53422c31f..ab299f4debfa 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -836,12 +836,11 @@ static int tc_main_link_setup(struct tc_data *tc)
> if (!tc->mode)
> return -EINVAL;
>
> - /* from excel file - DP0_SrcCtrl */
> - tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
> - DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
> - DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
> - /* from excel file - DP1_SrcCtrl */
> - tc_write(DP1_SRCCTRL, 0x00003083);
> + tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
> + /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
> + tc_write(DP1_SRCCTRL,
> + (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
> + ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
Wouldn't be better then to modify tc_srcctrl to support DP0 and DP1:
tc_write(DP0_SRCCTRL, tc_srcctrl(tc, 0));
tc_write(DP1_SRCCTRL, tc_srcctrl(tc, 1));
Just suggestion.
With or without this change:
Reviewed-by: Andrzej Hajda <a.hajda@xxxxxxxxxxx>
--
Regards
Andrzej
Regards
Andrzej
>
> rate = clk_get_rate(tc->refclk);
> switch (rate) {
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