>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, November 6, 2018 2:42 PM
>To: Srivatsa, Anusha <anusha.srivatsa@xxxxxxxxx>
>Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; dri-devel@xxxxxxxxxxxxxxxxxxxxx; Singh,
>Gaurav K <gaurav.k.singh@xxxxxxxxx>; Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>;
>Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
>Subject: Re: [v6 3/4] i915/dp/fec: Configure the Forward Error Correction bits.
>
>On Mon, Nov 05, 2018 at 03:31:49PM -0800, Anusha Srivatsa wrote:
>> If FEC is supported, the corresponding DP_TP_CTL register bits have to
>> be configured.
>>
>> The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register and
>> wait till FEC_STATUS in DP_TP_CTL[28] is 1.
>> Also add the warn message to make sure that the control register is
>> already active while enabling FEC.
>>
>> v2:
>> - Change commit message. Configure fec state after
>> link training (Manasi, Gaurav)
>> - Remove redundent checks (Manasi)
>> - Remove the registers that get added automagically (Anusha)
>>
>> v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
>>
>> v4: rebased.
>>
>> v5:
>> - Move the code to the proper spot, according to spec.(Ville)
>> - Use fec state as a check too.
>>
>> v6: Pass intel_encoder, instead of intel_dp. (Ville)
>>
>> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
>> Cc: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
>> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
>> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
>> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_ddi.c | 24 ++++++++++++++++++++++++
>> 2 files changed, 26 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 1a84e8f98e66..209b64d2f27a
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9148,6 +9148,7 @@ enum skl_power_gate {
>> #define _DP_TP_CTL_B 0x64140
>> #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
>> #define DP_TP_CTL_ENABLE (1 << 31)
>> +#define DP_TP_CTL_FEC_ENABLE (1 << 30)
>> #define DP_TP_CTL_MODE_SST (0 << 27)
>> #define DP_TP_CTL_MODE_MST (1 << 27)
>> #define DP_TP_CTL_FORCE_ACT (1 << 25)
>> @@ -9166,6 +9167,7 @@ enum skl_power_gate {
>> #define _DP_TP_STATUS_A 0x64044
>> #define _DP_TP_STATUS_B 0x64144
>> #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A,
>> _DP_TP_STATUS_B)
>> +#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
>> #define DP_TP_STATUS_IDLE_DONE (1 << 25)
>> #define DP_TP_STATUS_ACT_SENT (1 << 24)
>> #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>> b/drivers/gpu/drm/i915/intel_ddi.c
>> index 53a9b31e66a2..fad7385dbd76 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -3065,6 +3065,28 @@ static void intel_dp_sink_set_fec_ready(struct
>intel_dp *intel_dp,
>> DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n"); }
>>
>> +static void intel_ddi_enable_fec(struct intel_encoder *encoder,
>> + const struct intel_crtc_state *crtc_state) {
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> + enum port port = encoder->port;
>> + u32 val;
>> +
>> + /* FEC support exists for DP 1.4 only */
>
>No need for this comment here now since all the platform and sink checks
>already done while setting the the fec state.
Agreed.
>
>> + if (!crtc_state->fec_enable)
>> + return;
>> +
>> + val = I915_READ(DP_TP_CTL(port));
>> + val |= DP_TP_CTL_FEC_ENABLE;
>> + I915_WRITE(DP_TP_CTL(port), val);
>
>Do we need a POSTING_READ() here as well? It's used in case of disable fec in
>DP_TP_CTL.
>May be double check when we need it and when we don't.
I don't think we need POSTING_READ, the spec says "wait for FEC_STATUS in DP_TP_CTL[28] is 1. That is why after the i915_WRITE above, I am using intel_Wait_for_register().
Anusha
>Manasi
>
>> +
>> + if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
>> + DP_TP_STATUS_FEC_ENABLE_LIVE,
>> + DP_TP_STATUS_FEC_ENABLE_LIVE,
>> + 1))
>> + DRM_ERROR("Timed out waiting for FEC Enable Status\n"); }
>> +
>> static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state,
>> const struct drm_connector_state
>*conn_state) @@ -3110,6
>> +3132,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
>*encoder,
>> if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
>> intel_dp_stop_link_train(intel_dp);
>>
>> + intel_ddi_enable_fec(encoder, crtc_state);
>> +
>> icl_enable_phy_clock_gating(dig_port);
>>
>> if (!is_mst)
>> --
>> 2.19.1
>>
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