On Thu, Oct 25, 2018 at 05:09:42PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:34PM -0700, Manasi Navare wrote:
> > DSC PPS secondary data packet infoframes are filled with
> > DSC picure parameter set metadata according to the DSC standard.
> > These infoframes are sent to the sink device and used during DSC
> > decoding.
> >
> > v2:
> > * Rebase ond drm-tip
> >
> > Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> > Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> > Cc: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> > Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> > Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> > index b0fc716bbbfd..4b4b812d68f3 100644
> > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > @@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
> > }
> > }
> >
> > +static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
>
> const crtc_state
Changing this to const crtc_state started giving me an error when I get the
struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
So this is making me think that since dp_dsc_cfg is written during compute_config,
and there on we just read it, we dont need to pass *vdsc_cfg , we can
just pass the struct directly right?
Manasi
>
> s/send/write/ ?
>
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > + struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
> > + struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
> > +
> > + /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
> > + drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
> > +
> > + /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
> > + drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
> > +
> > + intel_dig_port->write_infoframe(encoder, crtc_state,
> > + DP_SDP_PPS, &dp_dsc_pps_sdp,
> > + sizeof(dp_dsc_pps_sdp));
> > +}
> > +
> > void intel_dsc_enable(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -997,5 +1016,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> >
> > intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
> >
> > + intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
> > +
> > return;
> > }
> > --
> > 2.18.0
>
> --
> Ville Syrjälä
> Intel
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