Comment # 13
on bug 108493
from Alex Deucher
(In reply to Timur Kristóf from comment #9) > OD_MCLK: > 0: 300MHz 750mV > 1: 1000MHz 800mV > 2: 1750MHz 900mV This is vddc. > [DEFAULT] ATOM_MCLK_ENTRY Array > ---- > > Entry: 0 > Frequency: 300 MHz. > Voltage:. 1000 MV > Entry: 1 > Frequency: 1000 MHz. > Voltage:. 1000 MV > Entry: 2 > Frequency: 1750 MHz. > Voltage:. 1000 MV > ---- This is mvdd. these are not the same voltages. The pp_od_clk_voltage interface only allows you to adjust vddc. The vddc values match what is in the vbios for your card.
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