Hi Russell, thanks for looking at the RFC ! > Given what's in the documentation, I'd opt for it describing the > edge that the output data changes, not the latch edge. With that > interpretation, the existing code is correct. The clock polarity is reversed in Freescale's non-mainline fbdev code, which we were using previously, contributing to the confusion. Yes, I think your interpretation is the correct one. Let's double-check. Suppose we set this bus flag in the panel/mode definition: drm/drm_connector.h: /* drive data on pos. edge */ #define DRM_BUS_FLAG_PIXDATA_POSEDGE (1<<2) According to your interpretation, this means we're asking the data to change on the positive edge, and be stable on the negative edge. Correct? then clk_pol == 1: drivers/gpu/drm/imx/ipuv3-crtc.c: sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE); then DI_GENERAL bit 17 is set: drivers/gpu/ipu-v3/ipu-di.c: if (sig->clk_pol) di_gen |= DI_GEN_POLARITY_DISP_CLK; and data is stable on the pixel clock's falling edge, as we observed on the oscilloscope. All good. Thank you ! _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
