On Wed, Oct 24, 2018 at 11:34 PM Maxime Ripard
<maxime.ripard@xxxxxxxxxxx> wrote:
>
> On Tue, Oct 23, 2018 at 09:20:22PM +0530, Jagan Teki wrote:
> > Some NKM PLLs doesn't work well when their output clock rate is set below
> > certain rate.
> >
> > So, add support for minimal rate for relevant PLLs.
> >
> > Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx>
> > ---
> > Changes for v2:
> > - new patch
> >
> > drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
> > drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> > index 841840e35e61..d17539dc88dd 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> > @@ -125,6 +125,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> > if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > rate *= nkm->fixed_post_div;
> >
> > + if (rate < nkm->min_rate) {
> > + rate = nkm->min_rate;
> > + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > + rate /= nkm->fixed_post_div;
>
> I'm not sure this is right. Is the post divider taken into account to
> calculate the minimum, or is the minimum on the rate before the fixed
> post divider.
Since we are returning from here, we need to take care post div which
is actually doing at the end of round_rate.
>
> How did you test this?
I've not used this on PLL_MIPI atleast, so I didn't test this.
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