From: Bin Meng
> Sent: 08 October 2018 13:34
> Hi David,
>
> On Mon, Oct 8, 2018 at 6:06 PM David Laight <David.Laight@xxxxxxxxxx> wrote:
> >
> > From: Bin Meng
> > > Sent: 08 October 2018 10:44
> > ...
> > > Correct, disable the shared interrupt line keeps all devices using
> > > that line from working, which is current kernel's behavior w/o this
> > > quirk handling: it disables the (shared) interrupt line after 100.000+
> > > generated interrupts. But the side effect is that other devices become
> > > unusable after that (eg: USB devices which share the same interrupt
> > > line with the Intel GPU). That's why the original commit, f67fd55fa96f
> > > ("PCI: Add quirk for still enabled interrupts on Intel Sandy Bridge
> > > GPUs") disables the GPU's interrupt directly, which should really be
> > > done by the VGA BIOS itself (a buggy VBIOS!).
> >
> > Shouldn't the kernel just disable all PCI(e) interrupts by writing
> > 1 to the config space control register bit during grope?
> > Can it ever by right for this to be set?
> >
>
> Do you mean PCI_COMMAND_INTX_DISABLE bit of the command register in
> the configuration space? Setting this bit indeed could disable the
> INTx interrupt, but it does not work for all PCI devices as this bit
> was introduced in PCI spec v2.3.
That's the one I was thinking of.
If it was introduced in v2.3 it explains why it is a 'disable' bit.
The v2.2 spec I just found doesn't seem to say anything about the
'reserved' bits. I guess the values are ignored (and probobly read
back as zeros).
In any case it should be implemented by the VGA devices in question.
I guess the kernel should also ensure that MSI and MSI-X interrupts
are also all disabled.
David
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