https://bugzilla.kernel.org/show_bug.cgi?id=201275 --- Comment #23 from quirin.blaeser@xxxxxxxxxx --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c (v4.18.12) There is a lot of work to do: 230 for (i = 0; i < dc_clks->num_levels; i++) { 231 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]); 232 /* translate 10kHz to kHz */ 233 dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10; 234 } 257 for (i = 0; i < clk_level_info->num_levels; i++) { 258 DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz); 259 /* translate 10kHz to kHz */ 260 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10; 261 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us; 262 } and maybe 306 /* Translate 10 kHz to kHz. */ 307 validation_clks.engine_max_clock *= 10; 308 validation_clks.memory_max_clock *= 10; since 2017-09-12 15:58:20 bool dm_pp_get_clock_levels_by_type_with_voltage( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels_with_voltage *clk_level_info) { /* TODO: to be implemented */ return false; } bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) { /* TODO: to be implemented */ return false; } bool dm_pp_apply_power_level_change_request( const struct dc_context *ctx, struct dm_pp_power_level_change_request *level_change_req) { /* TODO: to be implemented */ return false; } bool dm_pp_apply_clock_for_voltage_request( const struct dc_context *ctx, struct dm_pp_clock_for_voltage_req *clock_for_voltage_req) { /* TODO: to be implemented */ return false; } bool dm_pp_get_static_clocks( const struct dc_context *ctx, struct dm_pp_static_clock_info *static_clk_info) { /* TODO: to be implemented */ return false; } -- You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
