On Tue, Sep 18, 2018 at 06:21:59PM +0100, Eric Engestrom wrote:
> All the other vendors use the format
> DRM_FORMAT_MOD_{SAMSUNG,QCOM,VIVANTE,NVIDIA,BROADCOM,ARM}_* for their
> modifiers, except Intel.
>
> Suggested-by: Gerd Hoffmann <kraxel@xxxxxxxxxx>
> Signed-off-by: Eric Engestrom <eric.engestrom@xxxxxxxxx>
I think it'd be good to add why you want this (easier to parse in tooling,
or something like that was what you said on irc). With that addressed,
Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx> on both patches.
Probably best if you get i915 maintainers to merge both through drm-intel.
-Daniel
> ---
> include/uapi/drm/drm_fourcc.h | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 139632b871816f9e3dad..170a562223387687592a 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -271,7 +271,8 @@ extern "C" {
> * sharing. It exists since on a given platform it does uniquely identify the
> * layout in a simple way for i915-specific userspace.
> */
> -#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
> +#define DRM_FORMAT_MOD_INTEL_X_TILED fourcc_mod_code(INTEL, 1)
> +#define I915_FORMAT_MOD_X_TILED DRM_FORMAT_MOD_INTEL_X_TILED
>
> /*
> * Intel Y-tiling layout
> @@ -286,7 +287,8 @@ extern "C" {
> * sharing. It exists since on a given platform it does uniquely identify the
> * layout in a simple way for i915-specific userspace.
> */
> -#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
> +#define DRM_FORMAT_MOD_INTEL_Y_TILED fourcc_mod_code(INTEL, 2)
> +#define I915_FORMAT_MOD_Y_TILED DRM_FORMAT_MOD_INTEL_Y_TILED
>
> /*
> * Intel Yf-tiling layout
> @@ -301,7 +303,8 @@ extern "C" {
> * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
> * in pixel depends on the pixel depth.
> */
> -#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
> +#define DRM_FORMAT_MOD_INTEL_Yf_TILED fourcc_mod_code(INTEL, 3)
> +#define I915_FORMAT_MOD_Yf_TILED DRM_FORMAT_MOD_INTEL_Yf_TILED
>
> /*
> * Intel color control surface (CCS) for render compression
> @@ -320,8 +323,10 @@ extern "C" {
> * But that fact is not relevant unless the memory is accessed
> * directly.
> */
> -#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
> -#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
> +#define DRM_FORMAT_MOD_INTEL_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
> +#define I915_FORMAT_MOD_Y_TILED_CCS DRM_FORMAT_MOD_INTEL_Y_TILED_CCS
> +#define DRM_FORMAT_MOD_INTEL_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
> +#define I915_FORMAT_MOD_Yf_TILED_CCS DRM_FORMAT_MOD_INTEL_Yf_TILED_CCS
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> --
> Cheers,
> Eric
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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