Re: [PATCH 6/9] drm/amdgpu: add freesync ioctl

Christian König <ckoenig.leichtzumerken@xxxxxxxxx> · Wed, 12 Sep 2018 09:11:59 +0200

Am 11.09.2018 um 21:17 schrieb Alex Deucher:
On Tue, Sep 11, 2018 at 1:59 PM Kazlauskas, Nicholas
<nicholas.kazlauskas@xxxxxxx> wrote:
On 09/11/2018 01:51 PM, Christian König wrote:
Am 11.09.2018 um 18:13 schrieb Nicholas Kazlauskas:
From: Harry Wentland <harry.wentland@xxxxxxx>

Add the ioctl to enable/disable freesync.
Why do we still need this now that we have the DRM CRTC properties?
These patches were already merged into amd-staging-drm-next so we felt
it was best to just base the existing ones off of this work to keep
things consistent.

The later patches in the series remove most of it but it looks like some
of ioctl stuff itself was missed in amdgpu. It could probably use
another patch on top of this to finish cleaning it up.
You might want to just revert the relevant commits in
amd-staging-drm-next as the starting point for this patch set so that
what we eventually upstream is clean.  Better yet, base it on this
branch:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.20-wip
Which is basically amd-staging-drm-next without all the non-upstream stuff.

Yes, completely agree.

For review it is certainly better to have a clean history based on some 
upstream branch, especially when you add common stuff like in this patchset.

Regards,
Christian.


Alex

Christian.

Signed-off-by: Harry Wentland <harry.wentland@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h              |  3 +++
   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c      | 15 +++++++++++++++
   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c          |  3 ++-
   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    |  4 ++++
   include/uapi/drm/amdgpu_drm.h                    | 16 ++++++++++++++++
   5 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 447c4c7a36d6..95af917007f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1193,6 +1193,9 @@ int amdgpu_cs_wait_fences_ioctl(struct
drm_device *dev, void *data,
   int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
                   struct drm_file *filp);
+int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
+                  struct drm_file *filp);
+
   /* VRAM scratch page for HDP bug, default vram page */
   struct amdgpu_vram_scratch {
       struct amdgpu_bo        *robj;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 642b47c5f4b8..7d6a36bca9dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -894,3 +894,18 @@ int amdgpu_display_crtc_idx_to_irq_type(struct
amdgpu_device *adev, int crtc)
           return AMDGPU_CRTC_IRQ_NONE;
       }
   }
+
+int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
+                  struct drm_file *filp)
+{
+    int ret = -EPERM;
+    struct amdgpu_device *adev = dev->dev_private;
+
+    if (adev->mode_info.funcs->notify_freesync)
+        ret = adev->mode_info.funcs->notify_freesync(dev,data,filp);
+    else
+        DRM_DEBUG("amdgpu no notify_freesync ioctl\n");
+
+    return ret;
+}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bd98cc5fb97b..5b26e0447221 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1099,7 +1099,8 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
       DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA,
amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
       DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
       DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
-    DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW)
+    DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
+    DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_display_freesync_ioctl,
DRM_MASTER)
   };
   const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8be3028850b6..56598ed53123 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1584,6 +1584,7 @@ static void dm_bandwidth_update(struct
amdgpu_device *adev)
   static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
                   struct drm_file *filp)
   {
+    struct drm_amdgpu_freesync *args = data;
       struct drm_atomic_state *state;
       struct drm_modeset_acquire_ctx ctx;
       struct drm_crtc *crtc;
@@ -1593,6 +1594,9 @@ static int amdgpu_notify_freesync(struct
drm_device *dev, void *data,
       uint8_t i;
       bool enable = false;
+    if (args->op == AMDGPU_FREESYNC_FULLSCREEN_ENTER)
+        enable = true;
+
       drm_modeset_acquire_init(&ctx, 0);
       state = drm_atomic_state_alloc(dev);
diff --git a/include/uapi/drm/amdgpu_drm.h
b/include/uapi/drm/amdgpu_drm.h
index 1ceec56de015..94444eeba55b 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -54,6 +54,8 @@ extern "C" {
   #define DRM_AMDGPU_VM            0x13
   #define DRM_AMDGPU_FENCE_TO_HANDLE    0x14
   #define DRM_AMDGPU_SCHED        0x15
+/* not upstream */
+#define DRM_AMDGPU_FREESYNC            0x5d
   #define DRM_IOCTL_AMDGPU_GEM_CREATE    DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
   #define DRM_IOCTL_AMDGPU_GEM_MMAP    DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -71,6 +73,7 @@ extern "C" {
   #define DRM_IOCTL_AMDGPU_VM        DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_VM, union drm_amdgpu_vm)
   #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
   #define DRM_IOCTL_AMDGPU_SCHED        DRM_IOW(DRM_COMMAND_BASE +
DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
+#define DRM_IOCTL_AMDGPU_FREESYNC    DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
   /**
    * DOC: memory domains
@@ -987,6 +990,19 @@ struct drm_amdgpu_info_vce_clock_table {
   #define AMDGPU_FAMILY_AI            141 /* Vega10 */
   #define AMDGPU_FAMILY_RV            142 /* Raven */
+/*
+ * Definition of free sync enter and exit signals
+ * We may have more options in the future
+ */
+#define AMDGPU_FREESYNC_FULLSCREEN_ENTER        1
+#define AMDGPU_FREESYNC_FULLSCREEN_EXIT         2
+
+struct drm_amdgpu_freesync {
+    __u32 op;            /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */
+                        /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */
+    __u32 spare[7];
+};
+
   #if defined(__cplusplus)
   }
   #endif
Nicholas Kazlauskas
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