On Mon, Sep 10, 2018 at 10:55 AM Lee, Shawn C <shawn.c.lee@xxxxxxxxx> wrote: > > Only specific N value (0x8000) would be acceptable for LG > LP140WF6-SPM1 eDP panel which is running at asynchronous > clock mode. With the other N value, it will enter BITS mode > and display black screen. This patch series set constant N > value for specific sink/branch device that would cover > similar issue. Is this an explicit requirement of the panel itself or just a workaround for for a PLL limitation on a particular GPU? For example, due to hw design and electrical characteristics, certain divider combinations may not be viable on certain asics. If that's the case, shouldn't this be handled in an asic specific manor? If it's a requirement of the panel itself, ignore me and carry on. Alex > > Cc: Jani Nikula <jani.nikula@xxxxxxxxx> > Cc: Cooper Chiou <cooper.chiou@xxxxxxxxx> > Cc: Matt Atwood <matthew.s.atwood@xxxxxxxxx> > Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> > Cc: Clint Taylor <clinton.a.taylor@xxxxxxxxx> > > Lee, Shawn C (3): > drm: Add support for device_id based detection. > drm: Change limited M/N quirk to constant N quirk. > drm: add LG eDP panel to quirk database > > drivers/gpu/drm/drm_dp_helper.c | 17 ++++++++++++++++- > drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++--------------- > drivers/gpu/drm/i915/intel_display.h | 2 +- > drivers/gpu/drm/i915/intel_dp.c | 8 ++++---- > drivers/gpu/drm/i915/intel_dp_mst.c | 6 +++--- > include/drm/drm_dp_helper.h | 6 +++--- > 6 files changed, 40 insertions(+), 27 deletions(-) > > -- > 2.7.4 > > _______________________________________________ > dri-devel mailing list > dri-devel@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
