On Fri, Sep 7, 2018 at 5:55 AM, Bas Nieuwenhuizen <bas@xxxxxxxxxxxxxxxxxxx> wrote: > On Fri, Sep 7, 2018 at 6:51 AM Marek Olšák <maraeo@xxxxxxxxx> wrote: >> >> Hopefully this answers some questions. >> >> Other parameters that affect tiling layouts are GB_ADDR_CONFIG (all >> chips) and MC_ARB_RAMCFG (GFX6-8 only), and those vary with each chip. > > For GFX6-GFX8: > From GB_ADDR_CONFIG addrlib only uses the pipe interleave bytes which > are 0 (=256 bytes) for all AMDGPU HW (and on GFX9 addrlib even asserts > on that). From MC_ARB_RAMCFG addrlib reads the number of banks and > ranks, calculates the number of logical banks from it, but then does > not use it. (Presumably because it is the same number as the number of > banks in the tiling table entry?) Some bits gets used by the kernel > (memory row size), but those get encoded in the tile split of the > tiling table, i.e. we do not need the separate bits. > > for GFX9, only the DCC meta surface seems to depend on GB_ADDR_CONFIG > (except the aforementioned pipe interleave bytes) which are constant. On GFX9, addrlib in Mesa uses most fields from GB_ADDR_CONFIG. GB_ADDR_CONFIG defines the tiling formats. On older chips, addrlib reads some fields from GB_ADDR_CONFIG and uses the chip identification for others like the number of pipes, even though GB_ADDR_CONFIG has the information too. Marek _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
