[Bug 45921] [r300g, bisected] Multiple piglit regression after winsys/radeon: hook up the new DRM_RADEON_GEM_WAIT ioctl

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https://bugs.freedesktop.org/show_bug.cgi?id=45921

Pavel Ondračka <pavel.ondracka@xxxxxxxx> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |bryancain3+fdo@xxxxxxxxx

--- Comment #5 from Pavel Ondračka <pavel.ondracka@xxxxxxxx> 2012-02-11 05:59:42 PST ---
Marek you were right with the glsl_to_tgsi cause. It indeed seems majority of the commits fails due to some glsl_to_tgsi changes. 

fs-any-bvec2-using-if
fs-op-ne-mat2-mat2-using-if
fs-op-ne-mat2x3-mat2x3-using-if
fs-op-ne-mat2x4-mat2x4-using-if
regressed with:
a43f68810a347f3e952a0bc401be6edb91e1baea is the first bad commit
commit a43f68810a347f3e952a0bc401be6edb91e1baea
Author: Bryan Cain <bryancain3@xxxxxxxxx>
Date:   Sat Aug 20 13:26:12 2011 -0500

    glsl_to_tgsi: implement ir_unop_any using DP4 w/saturate or DP4 w/SLT

    This is a port of commit 92ca560d68e8 to glsl_to_tgsi, with integer support
    added.



glsl1-inequality (vec2, pass)
fs-op-ne-bvec2-bvec2-using-if
fs-op-ne-ivec2-ivec2-using-if
fs-op-ne-vec2-vec2-using-if
regressed with:
f3dce133f0422c42ca61f07f488237107efc30e6 is the first bad commit
commit f3dce133f0422c42ca61f07f488237107efc30e6
Author: Bryan Cain <bryancain3@xxxxxxxxx>
Date:   Sat Aug 20 13:56:06 2011 -0500

    glsl_to_tgsi: implement ir_binop_any_nequal using DP4 w/saturate or DP4 w/SLT

    Implement the any() part of the operation the same way regular ir_unop_any
    is implemented.

    This is a port of commit e7bf096e8b04 to glsl_to_tgsi, with added integer
    support.


The rest of the tests (glsl-fs-discard-02, glsl-max-varyings and glsl-vs-loop-redundant-condition) regressed in another (probably 3 different) places. I'll get
to them later.  BTW this may be the worst bisect I've ever done.

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