Re: [PATCH v4 02/11] clk: sunxi-ng: a64: Add max. rate constraint to video PLLs

[Sergey Suloev <ssuloev@xxxxxxxxxxxxx>]

Hi,

On 09/05/2018 10:16 AM, Maxime Ripard wrote:

On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote:

Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.

Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
other SoCs, so more faith is put in BSP clock driver.

Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx>

Applied, thanks!
Maxime

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what source tree this patch is supposed to apply for ?
I can't find  the SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX declaration in 4.19

Thank you
Sergey

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