On Tue, Sep 04, 2018 at 12:40:49PM +0800, Icenowy Zheng wrote: > From: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > > Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent. > > Include the macro on dt-bindings so-that the same can be used > while defining CCU clock phandles. > > Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx> Applied, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Attachment:
signature.asc
Description: PGP signature
_______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
