>-----Original Message-----
>From: Navare, Manasi D
>Sent: Monday, July 30, 2018 7:13 PM
>To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>Cc: ville.syrjala@xxxxxxxxxxxxxxx; jani.nikula@xxxxxxxxxxxxxxx; Srivatsa, Anusha
><anusha.srivatsa@xxxxxxxxx>; Singh, Gaurav K <gaurav.k.singh@xxxxxxxxx>; dri-
>devel@xxxxxxxxxxxxxxxxxxxxx; Navare, Manasi D <manasi.d.navare@xxxxxxxxx>
>Subject: [PATCH 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth
>constants
>
>From: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
>
>DSC specification defines linebuf_depth which contains the line buffer bit depth
>used to generate the bitstream.
>These values are defined as per Table 4.1 in DSC 1.2 spec
>
>v2 (From Manasi):
>* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
>
>Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
>Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
>Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>Signed-off-by: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
>Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
>---
> include/drm/drm_dsc.h | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index
>30adc15..4cfcd03 100644
>--- a/include/drm/drm_dsc.h
>+++ b/include/drm/drm_dsc.h
>@@ -56,6 +56,9 @@
> #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
> #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
> #define DSC_PPS_NATIVE_420_SHIFT 1
>+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
>+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
>+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
>
> /* Configuration for a single Rate Control model range */ struct
>dsc_rc_range_parameters {
>--
>2.7.4
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