On Fri, Jan 27, 2012 at 9:40 PM, Daniel Vetter <daniel.vetter@xxxxxxxx> wrote: > CEA actually specifies an interlaced mode with even vtotal and > supplies a diagram showing how this is supposed to work. > > Note that interlaced modes with an even vtotal seem to be a fairly > recent invention. All modelines lore I could dig up with googling says > that vtotal for interlaced modes _needs_ to be odd. But the even > modelines in CEA are not a spec-bug, there's a figure in CEA-861-E > called "Figure 5 Special Interlaced Video Format Timing (Even Vtotal)" > that explains how it's supposed to work. Furthermore intel Bspec > explicitly mentions that both odd and even interlaced vtotal are > supported (VTOTAL register in the south display engine of PCH split > chips). > > Cc: Adam Jackson <ajax@xxxxxxxxxx> > Signed-Off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> > --- Ajax? I'd like your ack/review on this. Thanks, Dave. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
