From: Sean Paul <seanpaul@xxxxxxxxxxxx> This patch adds a 70ms mystery delay to the bridge driver in enable. By experimentation, it seems like it can go anywhere up until we initiate semi-auto link training. If we don't have the delay, link training fails. I tried to root cause this as best I could, but neither the datasheet for the panel nor the bridge mention a delay of this magnitude in their timing requirements. So for now, add the mystery delay until someone figures out a better fix. Changes in v3: - Added to the set Cc: Sandeep Panda <spanda@xxxxxxxxxxxxxx> Signed-off-by: Sean Paul <seanpaul@xxxxxxxxxxxx> --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index d3e27e52ea759..f8a931cf3665e 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -458,6 +458,18 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) unsigned int val; int ret; + /* + * FIXME: + * This 70ms was found necessary by experimentation. If it's not + * present, link training fails. It seems like it can go anywhere from + * pre_enable() up to semi-auto link training initiation below. + * + * Neither the datasheet for the bridge nor the panel tested mention a + * delay of this magnitude in the timing requirements. So for now, add + * the mystery delay until someone figures out a better fix. + */ + msleep(70); + /* DSI_A lane config */ val = CHA_DSI_LANES(4 - pdata->dsi->lanes); regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, -- Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
