The VESA specification suggests a 2.2 ms timeout on DDC channels.
Use exactly that (as the i915 driver does) instead of hard-coding a
jiffy count.
Signed-off-by: Jean Delvare <jdelvare@xxxxxxx>
Reviewed-by: Keith Packard <keithp@xxxxxxxxxx>
Cc: Dave Airlie <airlied@xxxxxxxxx>
Cc: Alex Deucher <alexdeucher@xxxxxxxxx>
---
Already sent on: 2011-10-21.
drivers/gpu/drm/radeon/radeon_i2c.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
--- linux-3.3-rc1.orig/drivers/gpu/drm/radeon/radeon_i2c.c 2012-01-28 10:37:51.722069517 +0100
+++ linux-3.3-rc1/drivers/gpu/drm/radeon/radeon_i2c.c 2012-01-28 10:39:26.996070929 +0100
@@ -925,9 +925,7 @@ struct radeon_i2c_chan *radeon_i2c_creat
i2c->algo.bit.getsda = get_data;
i2c->algo.bit.getscl = get_clock;
i2c->algo.bit.udelay = 10;
- /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
- * make this, 2 jiffies is a lot more reliable */
- i2c->algo.bit.timeout = 2;
+ i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */
i2c->algo.bit.data = i2c;
ret = i2c_bit_add_bus(&i2c->adapter);
if (ret) {
--
Jean Delvare
Suse L3
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