Comment # 1
on bug 107296
from Paul Menzel
In today’s drm-tip this is:
[ 20.149515] WARNING: CPU: 0 PID: 347 at
drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:1372
dcn_bw_update_from_pplib+0x16b/0x280 [amdgpu]
It looks like this is `BREAK_TO_DEBUGGER()` [1], which is defined as `#define
BREAK_TO_DEBUGGER() ASSERT(0)`.
```
/* TODO: This is not the proper way to obtain
fabric_and_dram_bandwidth, should be min(fclk, memclk) */
res = dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
if (res)
res = verify_clock_values(&fclks);
if (res) {
ASSERT(fclks.num_levels >= 3);
dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 *
(fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
dc->dcn_soc->number_of_channels *
(fclks.data[fclks.num_levels -
(fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
* ddr4_dram_factor_single_Channel / 1000.0;
dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
dc->dcn_soc->number_of_channels *
(fclks.data[fclks.num_levels - 2].clocks_in_khz
/ 1000.0)
* ddr4_dram_factor_single_Channel / 1000.0;
dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
dc->dcn_soc->number_of_channels *
(fclks.data[fclks.num_levels - 1].clocks_in_khz
/ 1000.0)
* ddr4_dram_factor_single_Channel / 1000.0;
} else
BREAK_TO_DEBUGGER();
```
So, either `dm_pp_get_clock_levels_by_type_with_voltage()` or
`verify_clock_values(&fclks)` returns 0.
[1]:
https://cgit.freedesktop.org/drm-tip/tree/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c#n1372
You are receiving this mail because:
- You are the assignee for the bug.
_______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
