Here's a couple of patches that fix some bpc (bits per component) computation issues with DisplayPort. The problem was that the DisplayPort code tried to figure out the 'current' bpc by looking at the bpp stored in an associated crtc, but that was never right (as described in the message for the first patch). The first patch assumes that the display will run at 8bpc (24bpp) if the link has enough bandwidth, otherwise at 6bpc (18bpp). This is essentially what the existing code ends up doing at boot time; modes are computed before any crtc is assigned, so intel_dp_link_required would have used 24bpp for bandwidth computations. The second patch allows for arbitrary bpc values, computing the display bpc in both intel_dp_mode_fixup and the two crtc_mode_set functions. Obviously doing the computation once would be nice, but there isn't an obvious place to stick the result between those two functions as the bpc computation is also needed for non-DP encoders. This should fix problems where display port doesn't come back after resume for panels which need 6bpc modes. -- keith.packard@xxxxxxxxx _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
