tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-4.19-wip
head: 638d758f0bb28342123d87dbd8a4190a55e74771
commit: 522e6b434a61f8be910560969386a2b3ce113c1b [93/102] drm/amd/display: Initialize data structure for DalMpVisualConfirm.
config: x86_64-randconfig-g0-07132339 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
git checkout 522e6b434a61f8be910560969386a2b3ce113c1b
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function 'dcn10_update_mpcc':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1854:9: warning: missing braces around initializer [-Wmissing-braces]
struct mpcc_blnd_cfg blnd_cfg = {0};
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1854:9: warning: (near initialization for 'blnd_cfg.black_color') [-Wmissing-braces]
Cyclomatic Complexity 3 include/linux/string.h:memset
Cyclomatic Complexity 4 include/linux/string.h:memcmp
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:dc_fixpt_from_int
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:dc_fixpt_neg
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:dc_fixpt_abs
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:dc_fixpt_lt
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:dc_fixpt_floor
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:dm_read_reg_func
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:dm_write_reg_func
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:bios_golden_init
Cyclomatic Complexity 6 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:false_optc_underflow_wa
Cyclomatic Complexity 8 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:patch_address_for_sbs_tb_stereo
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_update_plane_addr
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:program_gamut_remap
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:program_csc_matrix
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_program_output_csc
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:is_lower_pipe_tree_visible
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:is_upper_pipe_tree_visible
Cyclomatic Complexity 6 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:is_pipe_tree_visible
Cyclomatic Complexity 6 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_get_surface_visual_confirm_color
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:update_scaler
Cyclomatic Complexity 6 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:find_top_pipe_for_stream
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:set_drr
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:get_position
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:set_static_screen_control
Cyclomatic Complexity 7 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_config_stereo_parameters
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_setup_stereo
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_dummy_display_power_gating
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_update_pending_status
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_set_cursor_position
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_set_cursor_attribute
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:log_mpc_crc
Cyclomatic Complexity 6 drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:dc_fixpt_sub
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:get_hubp_by_inst
Cyclomatic Complexity 19 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_hw_wa_force_recovery
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:dc_fixpt_mul_int
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:fixed_point_to_int_frac
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:enable_power_gating_plane
Cyclomatic Complexity 10 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:hubp_pg_control
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:undo_DEGVIDCN10_253_wa
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:apply_DEGVIDCN10_253_wa
Cyclomatic Complexity 10 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dpp_pg_control
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:power_on_plane
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:plane_atomic_power_down
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:plane_atomic_disable
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_disable_plane
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:mmhub_read_vm_system_aperture_settings
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:mmhub_read_vm_context0_settings
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_program_pte_vm
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:disable_vga
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:set_hdr_multiplier
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_pplib_apply_display_requirements
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:ready_shared_resources
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:optimize_shared_resources
Cyclomatic Complexity 8 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_blank_pixel_data
Cyclomatic Complexity 9 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_enable_stream_timing
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:wait_for_reset_trigger_to_occur
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_enable_per_frame_crtc_position_reset
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_enable_timing_synchronization
Cyclomatic Complexity 6 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_set_output_transfer_func
Cyclomatic Complexity 12 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_set_input_transfer_func
Cyclomatic Complexity 3 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_update_dchub
Cyclomatic Complexity 9 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:reset_back_end_for_pipe
Cyclomatic Complexity 7 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:reset_hw_ctx_wrap
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:print_microsec
Cyclomatic Complexity 13 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_log_hubp_states
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_log_hubbub_state
Cyclomatic Complexity 21 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_log_hw_state
Cyclomatic Complexity 7 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_verify_allow_pstate_change_high
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:hwss1_plane_atomic_disconnect
Cyclomatic Complexity 19 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_init_hw
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_enable_plane
Cyclomatic Complexity 6 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_wait_for_mpcc_disconnect
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_set_bandwidth
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_pipe_control_lock
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:is_rgb_cspace
Cyclomatic Complexity 11 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_update_mpcc
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:build_prescale_params
Cyclomatic Complexity 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:update_dpp
Cyclomatic Complexity 12 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:update_dchubp_dpp
Cyclomatic Complexity 4 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_program_pipe
Cyclomatic Complexity 5 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:program_all_pipe_in_tree
Cyclomatic Complexity 17 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_apply_ctx_for_surface
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:dcn10_hw_sequencer_construct
Cyclomatic Complexity 1 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:_GLOBAL__sub_I_65535_0_print_microsec
vim +1854 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c
1850
1851 static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1852 {
1853 struct hubp *hubp = pipe_ctx->plane_res.hubp;
> 1854 struct mpcc_blnd_cfg blnd_cfg = {0};
1855 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1856 int mpcc_id;
1857 struct mpcc *new_mpcc;
1858 struct mpc *mpc = dc->res_pool->mpc;
1859 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1860
1861
1862
1863 /* TODO: proper fix once fpga works */
1864
1865 if (dc->debug.surface_visual_confirm)
1866 dcn10_get_surface_visual_confirm_color(
1867 pipe_ctx, &blnd_cfg.black_color);
1868 else
1869 color_space_to_black_color(
1870 dc, pipe_ctx->stream->output_color_space,
1871 &blnd_cfg.black_color);
1872
1873 if (per_pixel_alpha)
1874 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1875 else
1876 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1877
1878 blnd_cfg.overlap_only = false;
1879 blnd_cfg.global_alpha = 0xff;
1880 blnd_cfg.global_gain = 0xff;
1881
1882 /* DCN1.0 has output CM before MPC which seems to screw with
1883 * pre-multiplied alpha.
1884 */
1885 blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1886 pipe_ctx->stream->output_color_space)
1887 && per_pixel_alpha;
1888
1889
1890 /*
1891 * TODO: remove hack
1892 * Note: currently there is a bug in init_hw such that
1893 * on resume from hibernate, BIOS sets up MPCC0, and
1894 * we do mpcc_remove but the mpcc cannot go to idle
1895 * after remove. This cause us to pick mpcc1 here,
1896 * which causes a pstate hang for yet unknown reason.
1897 */
1898 mpcc_id = hubp->inst;
1899
1900 /* If there is no full update, don't need to touch MPC tree*/
1901 if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
1902 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
1903 return;
1904 }
1905
1906 /* check if this MPCC is already being used */
1907 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1908 /* remove MPCC if being used */
1909 if (new_mpcc != NULL)
1910 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1911 else
1912 if (dc->debug.sanity_checks)
1913 mpc->funcs->assert_mpcc_idle_before_connect(
1914 dc->res_pool->mpc, mpcc_id);
1915
1916 /* Call MPC to insert new plane */
1917 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1918 mpc_tree_params,
1919 &blnd_cfg,
1920 NULL,
1921 NULL,
1922 hubp->inst,
1923 mpcc_id);
1924
1925 ASSERT(new_mpcc != NULL);
1926
1927 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1928 hubp->mpcc_id = mpcc_id;
1929 }
1930
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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