Am Donnerstag, den 12.07.2018, 16:37 +0300 schrieb Leonard Crestez:
> The imx6sl soc has gpu_2d and gpu_vg, no 3d support:
>
> etnaviv-gpu 2200000.gpu: model: GC320, revision: 5007
> etnaviv-gpu 2204000.gpu: model: GC355, revision: 1215
>
> The IP blocks are close enough to supported hardware that they "just
> work" with etnaviv and x11.
According to the kernel log above, they aren't just close enough, but
actually the same revision as the cores on the i.MX6Q.
> Signed-off-by: Leonard Crestez <leonard.crestez@xxxxxxx>
I think this DT is ordered by unit address, so both GPU nodes should
move to the end of the dts file, right?
With this fixed:
Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
>
> ---
> arch/arm/boot/dts/imx6sl.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> Tested by using yocto fsl community bsp built in "mainline" mode.
> This
> patch makes x11 start up and turning on drm.debug shows that the
> etnaviv
> driver is being used.
>
> I don't know if such a patch requires much more testing: all it
> really
> does is "describe the hardware".
>
> Patch is against shawguo/imx/dt, it depends on newly accepted
> commit 13211eec7b0e ("ARM: dts: imx6sl: Convert gpc to new bindings")
> This is only because of the way it references the PU power domain.
>
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi
> b/arch/arm/boot/dts/imx6sl.dtsi
> index a6bc21433839..49a56b4fd393 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -130,10 +130,30 @@
> cache-level = <2>;
> arm,tag-latency = <4 2 3>;
> arm,data-latency = <4 2 3>;
> };
>
> + gpu_2d: gpu@2200000 {
> + compatible = "vivante,gc";
> + reg = <0x02200000 0x4000>;
> + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
> + <&clks IMX6SL_CLK_GPU2D_OVG>;
> + clock-names = "bus", "core";
> + power-domains = <&pd_pu>;
> + };
> +
> + gpu_vg: gpu@2204000 {
> + compatible = "vivante,gc";
> + reg = <0x02204000 0x4000>;
> + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
> + <&clks IMX6SL_CLK_GPU2D_OVG>;
> + clock-names = "bus", "core";
> + power-domains = <&pd_pu>;
> + };
> +
> aips1: aips-bus@2000000 {
> compatible = "fsl,aips-bus", "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x02000000 0x100000>;
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