SoCs containing mdp5 or dpu have a MDSS top level wrapper which includes sub-blocks as mdp5/dpu, dsi, dp, hdmi etc. The MDSS top level wrapper manages common resources like common clocks, main power supply and interrupts for its sub-blocks. But current dpu driver implementation is based on a flat device hierarchy where MDSS/DPU HW blocks were represented by single device and DSI/DP etc. are represented as independent devices w/o any relationships b/t these nodes which doesn't model the HW associations precisely. A minimal MDSS and DPU controller device separation is done in following patch series [1] but currently both these devices match to a single driver which is getting probed two times and all the resources are still tied to DPU device. Moreover, all the power resource management in DPU driver is part of power_handle module which manages these resources via a custom implementation. Irq domain handling is part of DPU device, due to lack of a dedicated driver for MDSS top level wrapper device. This patch series aims at adding separate drivers for MDSS top level wrapper device and DPU child device. MDP5 device/driver is used as a reference for this refactoring effort. Both the drivers implement runtime_pm support for their power resource management. Child nodes can control common resources managed by parent device due to parent child relationship defined in dt. The top level MDSS device acts as an interrupt controller and manages hwirq mappings for its child devices. Inorder to add MDP5 and DPU specific MDSS driver implementation, this patch series also subclasses existing msm_mdss define. A helper interface (msm_mdss_funcs) is added to invoke the platform specific implementations. This change also corrects hw catalog offsets for all sub blocks present within DPU device. The offset are now defined wrt DPU base address (instead of using MDSS base address). Clock and Power handling code have been removed from dpu_power_handle since each device manages it's resources via runtime_pm. Now, since dpu_power_handle manages only bus scaling and power enable/disable notifications and it's usage is restricted to DPU driver only, moved dpu_power_handle code to DPU folder. This patch series depends on [1]. 1 - https://lists.freedesktop.org/archives/freedreno/2018-April/002354.html Rajesh Yadav (11): drm/msm: remove pm_runtime_enable call from msm_drv drm/msm/mdp5: subclass msm_mdss for mdp5 drm/msm/dpu: add MDSS top level driver for dpu drm/msm/dpu: create new platform driver for dpu device drm/msm/dpu: update dpu sub-block offsets wrt dpu base address drm/msm/dpu: use runtime_pm calls on dpu device drm/msm/dpu: remove clock management code from dpu_power_handle drm/msm/dpu: remove power management code from dpu_power_handle drm/msm/dp: remove dpu_power_handle calls from dp driver drm/msm/dpu: use runtime_pm calls in dpu_dbg drm/msm/dpu: move dpu_power_handle to dpu folder drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 106 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 51 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 19 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 77 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 47 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 11 - drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 48 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 354 +++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 301 ++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 694 +++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++++++ drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 +-- drivers/gpu/drm/msm/dp/dp_power.c | 32 +- drivers/gpu/drm/msm/dp/dp_power.h | 4 +- drivers/gpu/drm/msm/dpu_dbg.c | 18 +- drivers/gpu/drm/msm/dpu_dbg.h | 13 +- drivers/gpu/drm/msm/dpu_io_util.c | 55 + drivers/gpu/drm/msm/dpu_power_handle.c | 1075 -------------------- drivers/gpu/drm/msm/dpu_power_handle.h | 330 ------ drivers/gpu/drm/msm/msm_drv.c | 86 +- drivers/gpu/drm/msm/msm_drv.h | 10 +- drivers/gpu/drm/msm/msm_kms.h | 22 +- include/linux/dpu_io_util.h | 2 + 32 files changed, 1871 insertions(+), 2008 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.c delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.h -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
