[radeon-alex:drm-next-4.18-wip 260/261] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:1024 smu7_enable_sclk_mclk_dpm() warn: curly braces intended?

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tree:   git://people.freedesktop.org/~agd5f/linux.git drm-next-4.18-wip
head:   92fb37464bd2b759d74f33c3b90a27575601745d
commit: c5eb46b78b52a40bc91421f667130fa7f328e97a [260/261] drm/amd/powerplay: add specific changes for VEGAM in smu7_hwmgr.c

New smatch warnings:
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:1024 smu7_enable_sclk_mclk_dpm() warn: curly braces intended?

git remote add radeon-alex git://people.freedesktop.org/~agd5f/linux.git
git remote update radeon-alex
git checkout c5eb46b78b52a40bc91421f667130fa7f328e97a
vim +1024 drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c

599a7e9f Rex Zhu    2016-09-09  1014  
599a7e9f Rex Zhu    2016-09-09  1015  static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
599a7e9f Rex Zhu    2016-09-09  1016  {
599a7e9f Rex Zhu    2016-09-09  1017  	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
599a7e9f Rex Zhu    2016-09-09  1018  
599a7e9f Rex Zhu    2016-09-09  1019  	/* enable SCLK dpm */
599a7e9f Rex Zhu    2016-09-09  1020  	if (!data->sclk_dpm_key_disabled)
c5eb46b7 Eric Huang 2018-04-11  1021  		if (hwmgr->chip_id == CHIP_VEGAM)
c5eb46b7 Eric Huang 2018-04-11  1022  			smu7_disable_sclk_vce_handshake(hwmgr);
c5eb46b7 Eric Huang 2018-04-11  1023  
599a7e9f Rex Zhu    2016-09-09 @1024  		PP_ASSERT_WITH_CODE(
d3f8c0ab Rex Zhu    2017-09-20  1025  		(0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
599a7e9f Rex Zhu    2016-09-09  1026  		"Failed to enable SCLK DPM during DPM Start Function!",
599a7e9f Rex Zhu    2016-09-09  1027  		return -EINVAL);
599a7e9f Rex Zhu    2016-09-09  1028  
599a7e9f Rex Zhu    2016-09-09  1029  	/* enable MCLK dpm */
599a7e9f Rex Zhu    2016-09-09  1030  	if (0 == data->mclk_dpm_key_disabled) {
599a7e9f Rex Zhu    2016-09-09  1031  		if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
599a7e9f Rex Zhu    2016-09-09  1032  			smu7_disable_handshake_uvd(hwmgr);
c5eb46b7 Eric Huang 2018-04-11  1033  
599a7e9f Rex Zhu    2016-09-09  1034  		PP_ASSERT_WITH_CODE(
d3f8c0ab Rex Zhu    2017-09-20  1035  				(0 == smum_send_msg_to_smc(hwmgr,
599a7e9f Rex Zhu    2016-09-09  1036  						PPSMC_MSG_MCLKDPM_Enable)),
599a7e9f Rex Zhu    2016-09-09  1037  				"Failed to enable MCLK DPM during DPM Start Function!",
599a7e9f Rex Zhu    2016-09-09  1038  				return -EINVAL);
599a7e9f Rex Zhu    2016-09-09  1039  
c5eb46b7 Eric Huang 2018-04-11  1040  		if (hwmgr->chip_family != CHIP_VEGAM)
599a7e9f Rex Zhu    2016-09-09  1041  			PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
599a7e9f Rex Zhu    2016-09-09  1042  
86457c3b Rex Zhu    2017-09-14  1043  
86457c3b Rex Zhu    2017-09-14  1044  		if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
86457c3b Rex Zhu    2017-09-14  1045  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
86457c3b Rex Zhu    2017-09-14  1046  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
86457c3b Rex Zhu    2017-09-14  1047  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
86457c3b Rex Zhu    2017-09-14  1048  			udelay(10);
86457c3b Rex Zhu    2017-09-14  1049  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
86457c3b Rex Zhu    2017-09-14  1050  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
86457c3b Rex Zhu    2017-09-14  1051  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
86457c3b Rex Zhu    2017-09-14  1052  		} else {
599a7e9f Rex Zhu    2016-09-09  1053  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
599a7e9f Rex Zhu    2016-09-09  1054  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
599a7e9f Rex Zhu    2016-09-09  1055  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
599a7e9f Rex Zhu    2016-09-09  1056  			udelay(10);
c5eb46b7 Eric Huang 2018-04-11  1057  			if (hwmgr->chip_id == CHIP_VEGAM) {
c5eb46b7 Eric Huang 2018-04-11  1058  				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
c5eb46b7 Eric Huang 2018-04-11  1059  				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
c5eb46b7 Eric Huang 2018-04-11  1060  			} else {
599a7e9f Rex Zhu    2016-09-09  1061  				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
599a7e9f Rex Zhu    2016-09-09  1062  				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
c5eb46b7 Eric Huang 2018-04-11  1063  			}
599a7e9f Rex Zhu    2016-09-09  1064  			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
599a7e9f Rex Zhu    2016-09-09  1065  		}
86457c3b Rex Zhu    2017-09-14  1066  	}
599a7e9f Rex Zhu    2016-09-09  1067  
599a7e9f Rex Zhu    2016-09-09  1068  	return 0;
599a7e9f Rex Zhu    2016-09-09  1069  }
599a7e9f Rex Zhu    2016-09-09  1070  

:::::: The code at line 1024 was first introduced by commit
:::::: 599a7e9fe1b683d04f889d68f866f5548b1e0239 drm/amd/powerplay: implement smu7 hwmgr to manager asics with smu ip version 7.

:::::: TO: Rex Zhu <Rex.Zhu@xxxxxxx>
:::::: CC: Alex Deucher <alexander.deucher@xxxxxxx>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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