tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head: d64547a1cfa860e241b27723c88f86fa3d88d3d7
commit: 72f024dc00acedc55e654fa1acdf117e7936638b [18/22] drm/amd/display: add rq/dlg/ttu to dtn log
config: i386-randconfig-b0-04241142 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
git checkout 72f024dc00acedc55e654fa1acdf117e7936638b
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function 'dcn10_log_hw_state':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:304:10: warning: missing braces around initializer [-Wmissing-braces]
struct dcn_hubp_state s = {0};
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:304:10: warning: (near initialization for 's.dlg_attr') [-Wmissing-braces]
vim +304 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c
212
213 void dcn10_log_hw_state(struct dc *dc)
214 {
215 struct dc_context *dc_ctx = dc->ctx;
216 struct resource_pool *pool = dc->res_pool;
217 int i;
218
219 DTN_INFO_BEGIN();
220
221 dcn10_log_hubbub_state(dc);
222
223 DTN_INFO("HUBP: format addr_hi width height"
224 " rot mir sw_mode dcc_en blank_en ttu_dis underflow"
225 " min_ttu_vblank qos_low_wm qos_high_wm\n");
226 for (i = 0; i < pool->pipe_count; i++) {
227 struct hubp *hubp = pool->hubps[i];
228 struct dcn_hubp_state s;
229
230 hubp->funcs->hubp_read_state(hubp, &s);
231
232 DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
233 " %6d %8d %7d %8xh",
234 hubp->inst,
235 s.pixel_format,
236 s.inuse_addr_hi,
237 s.viewport_width,
238 s.viewport_height,
239 s.rotation_angle,
240 s.h_mirror_en,
241 s.sw_mode,
242 s.dcc_en,
243 s.blank_en,
244 s.ttu_disable,
245 s.underflow_status);
246 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
247 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
248 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
249 DTN_INFO("\n");
250 }
251 DTN_INFO("\n");
252
253 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
254 for (i = 0; i < pool->pipe_count; i++) {
255 struct mpcc_state s = {0};
256
257 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
258 if (s.opp_id != 0xf)
259 DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d\n",
260 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
261 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
262 s.idle);
263 }
264 DTN_INFO("\n");
265
266 DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
267 " h_bs h_be h_ss h_se hpol htot vtot underflow\n");
268
269 for (i = 0; i < pool->timing_generator_count; i++) {
270 struct timing_generator *tg = pool->timing_generators[i];
271 struct dcn_otg_state s = {0};
272
273 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
274
275 //only print if OTG master is enabled
276 if ((s.otg_enabled & 1) == 0)
277 continue;
278
279 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
280 " %5d %5d %5d %5d %9d\n",
281 tg->inst,
282 s.v_blank_start,
283 s.v_blank_end,
284 s.v_sync_a_start,
285 s.v_sync_a_end,
286 s.v_sync_a_pol,
287 s.v_total_max,
288 s.v_total_min,
289 s.v_total_max_sel,
290 s.v_total_min_sel,
291 s.h_blank_start,
292 s.h_blank_end,
293 s.h_sync_a_start,
294 s.h_sync_a_end,
295 s.h_sync_a_pol,
296 s.h_total,
297 s.v_total,
298 s.underflow_occurred_status);
299 }
300 DTN_INFO("\n");
301
302 for (i = 0; i < pool->pipe_count; i++) {
303 struct hubp *hubp = pool->hubps[i];
> 304 struct dcn_hubp_state s = {0};
305
306 if (!dc->current_state->res_ctx.pipe_ctx[i].stream)
307 continue;
308
309 hubp->funcs->hubp_read_state(hubp, &s);
310 DTN_INFO("RQ-DLG-TTU registers for HUBP%d:\n", i);
311 print_rq_dlg_ttu_regs(dc_ctx, &s);
312 DTN_INFO("\n");
313 }
314 DTN_INFO("\n");
315
316 log_mpc_crc(dc);
317
318 DTN_INFO_END();
319 }
320
---
0-DAY kernel test infrastructure Open Source Technology Center
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