Re: [PATCH 2/3] drm/vc4: Add color transformation matrix (CTM) support

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Hi Stefan,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on v4.16-rc4]
[also build test ERROR on next-20180316]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Stefan-Schake/drm-vc4-Atomic-color-management-support/20180318-120701
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/vc4/vc4_crtc.c: In function 'vc4_crtc_update_gamma_lut':
   drivers/gpu/drm/vc4/vc4_crtc.c:305:30: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
     struct drm_color_lut *lut = crtc->state->gamma_lut->data;
                                 ^~~~
   drivers/gpu/drm/vc4/vc4_crtc.c: In function 'vc4_crtc_update_ctm':
   drivers/gpu/drm/vc4/vc4_crtc.c:340:30: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
     struct drm_color_ctm *ctm = crtc->state->ctm->data;
                                 ^~~~
   In file included from drivers/gpu/drm/vc4/vc4_crtc.c:42:0:
>> drivers/gpu/drm/vc4/vc4_crtc.c:344:5: error: 'SCALER_OLEDCOEF2_R_TO_R_SHIFT' undeclared (first use in this function); did you mean 'SCALER_CSC0_COEF_CR_OFS_SHIFT'?
        SCALER_OLEDCOEF2_R_TO_R) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:343:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
        ^~~~~~~~~~~~~
   drivers/gpu/drm/vc4/vc4_crtc.c:344:5: note: each undeclared identifier is reported only once for each function it appears in
        SCALER_OLEDCOEF2_R_TO_R) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:343:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:344:5: error: 'SCALER_OLEDCOEF2_R_TO_R_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
        SCALER_OLEDCOEF2_R_TO_R) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
      WARN_ON((fieldval & ~field##_MASK) != 0);  \
      ^~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:343:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:346:5: error: 'SCALER_OLEDCOEF2_R_TO_G_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
        SCALER_OLEDCOEF2_R_TO_G) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
   drivers/gpu/drm/vc4/vc4_crtc.c:345:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:346:5: error: 'SCALER_OLEDCOEF2_R_TO_G_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_MASK'?
        SCALER_OLEDCOEF2_R_TO_G) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
      WARN_ON((fieldval & ~field##_MASK) != 0);  \
      ^~~~~~~
   drivers/gpu/drm/vc4/vc4_crtc.c:345:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:348:5: error: 'SCALER_OLEDCOEF2_R_TO_B_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_G_SHIFT'?
        SCALER_OLEDCOEF2_R_TO_B));
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
   drivers/gpu/drm/vc4/vc4_crtc.c:347:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:348:5: error: 'SCALER_OLEDCOEF2_R_TO_B_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_G_MASK'?
        SCALER_OLEDCOEF2_R_TO_B));
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
      WARN_ON((fieldval & ~field##_MASK) != 0);  \
      ^~~~~~~
   drivers/gpu/drm/vc4/vc4_crtc.c:347:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:12: error: 'SCALER_OLEDCOEF2' undeclared (first use in this function); did you mean 'SCALER_DISPCTRL2'?
     HVS_WRITE(SCALER_OLEDCOEF2,
               ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:61: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                                                ^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:351:5: error: 'SCALER_OLEDCOEF1_G_TO_R_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
        SCALER_OLEDCOEF1_G_TO_R) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
   drivers/gpu/drm/vc4/vc4_crtc.c:350:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:351:5: error: 'SCALER_OLEDCOEF1_G_TO_R_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_MASK'?
        SCALER_OLEDCOEF1_G_TO_R) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
      WARN_ON((fieldval & ~field##_MASK) != 0);  \
      ^~~~~~~
   drivers/gpu/drm/vc4/vc4_crtc.c:350:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:353:5: error: 'SCALER_OLEDCOEF1_G_TO_G_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF1_G_TO_R_SHIFT'?
        SCALER_OLEDCOEF1_G_TO_G) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
   drivers/gpu/drm/vc4/vc4_crtc.c:352:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:353:5: error: 'SCALER_OLEDCOEF1_G_TO_G_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF1_G_TO_R_MASK'?
        SCALER_OLEDCOEF1_G_TO_G) |
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
      WARN_ON((fieldval & ~field##_MASK) != 0);  \
      ^~~~~~~
   drivers/gpu/drm/vc4/vc4_crtc.c:352:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]),
        ^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:355:5: error: 'SCALER_OLEDCOEF1_G_TO_B_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF1_G_TO_G_SHIFT'?
        SCALER_OLEDCOEF1_G_TO_B));
        ^
   drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
    #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
                                          ^~~
   drivers/gpu/drm/vc4/vc4_crtc.c:354:5: note: in expansion of macro 'VC4_SET_FIELD'
        VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[7]),
        ^~~~~~~~~~~~~

vim +344 drivers/gpu/drm/vc4/vc4_crtc.c

   300	
   301	static void
   302	vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
   303	{
   304		struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 > 305		struct drm_color_lut *lut = crtc->state->gamma_lut->data;
   306		u32 length = crtc->state->gamma_lut->length / sizeof(*lut);
   307		u32 i;
   308	
   309		for (i = 0; i < length; i++) {
   310			vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
   311			vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
   312			vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
   313		}
   314	
   315		vc4_crtc_lut_load(crtc);
   316	}
   317	
   318	/* Converts a DRM S31.32 value to the HW S0.9 format. */
   319	static u16 vc4_crtc_s31_32_to_s0_9(u64 in)
   320	{
   321		u16 r;
   322	
   323		/* Sign bit. */
   324		r = in & BIT_ULL(63) ? BIT(9) : 0;
   325		/* We have zero integer bits so we can only saturate here. */
   326		if ((in & GENMASK_ULL(62, 32)) > 0)
   327			r |= GENMASK(8, 0);
   328		/* Otherwise take the 9 most important fractional bits. */
   329		else
   330			r |= (in >> 22) & GENMASK(8, 0);
   331		return r;
   332	}
   333	
   334	static void
   335	vc4_crtc_update_ctm(struct drm_crtc *crtc)
   336	{
   337		struct drm_device *dev = crtc->dev;
   338		struct vc4_dev *vc4 = to_vc4_dev(dev);
   339		struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
   340		struct drm_color_ctm *ctm = crtc->state->ctm->data;
   341	
 > 342		HVS_WRITE(SCALER_OLEDCOEF2,
 > 343			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
 > 344					SCALER_OLEDCOEF2_R_TO_R) |
 > 345			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
 > 346					SCALER_OLEDCOEF2_R_TO_G) |
 > 347			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
 > 348					SCALER_OLEDCOEF2_R_TO_B));
 > 349		HVS_WRITE(SCALER_OLEDCOEF1,
 > 350			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
 > 351					SCALER_OLEDCOEF1_G_TO_R) |
 > 352			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]),
 > 353					SCALER_OLEDCOEF1_G_TO_G) |
 > 354			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[7]),
 > 355					SCALER_OLEDCOEF1_G_TO_B));
 > 356		HVS_WRITE(SCALER_OLEDCOEF0,
 > 357			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[2]),
 > 358					SCALER_OLEDCOEF0_B_TO_R) |
 > 359			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[5]),
 > 360					SCALER_OLEDCOEF0_B_TO_G) |
 > 361			  VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[8]),
 > 362					SCALER_OLEDCOEF0_B_TO_B));
   363	
   364		/* Channel is 0-based but for DISPFIFO, 0 means disabled. */
 > 365		HVS_WRITE(SCALER_OLEDOFFS, VC4_SET_FIELD(vc4_crtc->channel + 1,
 > 366							 SCALER_OLEDOFFS_DISPFIFO));
   367	}
   368	
   369	/* Check if the CTM contains valid input.
   370	 *
   371	 * DRM exposes CTM with S31.32 scalars, but the HW only supports S0.9.
   372	 * We don't allow integer values >1, and 1 only without fractional part
   373	 * to handle the common 1.0 value.
   374	 */
   375	static int vc4_crtc_atomic_check_ctm(struct drm_crtc_state *state)
   376	{
 > 377		struct drm_color_ctm *ctm = state->ctm->data;
   378		u32 i;
   379	
   380		for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
   381			u64 val = ctm->matrix[i];
   382	
   383			val &= ~BIT_ULL(63);
   384			if ((val >> 32) > 1)
   385				return -EINVAL;
   386			if ((val >> 32) == 1 && (val & GENMASK_ULL(31, 0)) != 0)
   387				return -EINVAL;
   388		}
   389	
   390		return 0;
   391	}
   392	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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