On Thu, Mar 15, 2018 at 02:08:51PM -0700, matthew.s.atwood@xxxxxxxxx wrote: > From: Matt Atwood <matthew.s.atwood@xxxxxxxxx> > > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 > bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended > receiver capabilities. For panels that use this new feature wait interval > would be increased by 512 ms, when spec is max 16 ms. This behavior is > described in table 2-158 of DP 1.4 spec address 0000eh. > > With the introduction of DP 1.4 spec main link clock recovery was > standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value. > > To avoid breaking panels that are not spec compiant we now warn on > invalid values. > > V2: commit title/message, masking all 7 bits, warn on out of spec values. > V3: commit message, make link train clock recovery follow DP 1.4 spec. > V4: style changes > V5: typo > V6: print statement revisions, DP_REV to DPCD_REV, comment correction > V7: typo > V8: Style > > Signed-off-by: Matt Atwood <matthew.s.atwood@xxxxxxxxx> Tested-by: Benson Leung <bleung@xxxxxxxxxxxx> This version still passes link training on the panel with 8th bit set in DPCD 0x000e. Thanks, Benson -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@xxxxxxxxxx Chromium OS Project bleung@xxxxxxxxxxxx
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