On Mon, Mar 12, 2018 at 11:14:47PM -0700, John Hubbard wrote: > Yes, on NVIDIA GPUs, the Host/FIFO unit is limited to 40-bit addresses, so > things such as the following need to be below (1 << 40), and also accessible > to both CPU (user space) and GPU hardware. > -- command buffers (CPU user space driver fills them, GPU consumes them), > -- semaphores (here, a GPU-centric term, rather than OS-type: these are > memory locations that, for example, the GPU hardware might write to, in > order to indicate work completion; there are other uses as well), > -- a few other things most likely (this is not a complete list). Is that a 40-bit virtual address limit or physical address limit? I'm no longer sure who is addressing what memory through what mechanism ;-) _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
