Fix the compilation warnings flagged in display driver.
Signed-off-by: Sravanthi Kollukuduru <skolluku@xxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c | 4 ++--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 36a4795..ccf25a3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -592,15 +592,12 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
DPU_EVT32(kms->dev, stop_req, clk_rate);
- /* Temp change to avoid crash in clk_set_rate API. */
-#ifdef QCOM_DPU_SET_CLK
if (dpu_power_clk_set_rate(&priv->phandle,
kms->perf.clk_name, clk_rate)) {
DPU_ERROR("failed to set %s clock rate %llu\n",
kms->perf.clk_name, clk_rate);
return;
}
-#endif
kms->perf.core_clk_rate = clk_rate;
DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
index bb45477..e0d46c5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
@@ -374,7 +374,7 @@ static int validate_dma_cfg(struct dpu_reg_dma_setup_ops_cfg *cfg)
}
if (cfg->dma_buf->iova & GUARD_BYTES || !cfg->dma_buf->vaddr) {
- DRM_ERROR("iova not aligned to %zx iova %x kva %pK",
+ DRM_ERROR("iova not aligned to %zx iova %llx kva %pK",
ADDR_ALIGN, cfg->dma_buf->iova,
cfg->dma_buf->vaddr);
return -EINVAL;
@@ -433,7 +433,7 @@ static int validate_kick_off_v1(struct dpu_reg_dma_kickoff_cfg *cfg)
(WRITE_TRIGGER);
if (cfg->dma_buf->iova & GUARD_BYTES) {
- DRM_ERROR("Address is not aligned to %zx iova %x", ADDR_ALIGN,
+ DRM_ERROR("Address is not aligned to %zx iova %llx", ADDR_ALIGN,
cfg->dma_buf->iova);
return -EINVAL;
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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