Hi Matt, On Fri, Mar 02, 2018 at 02:25:58PM -0800, matthew.s.atwood@xxxxxxxxx wrote: > From: Matt Atwood <matthew.s.atwood@xxxxxxxxx> > > For panels that do not follow Display Port specifications mask off invalid > values for DP_TRAINING_AUX_RD_INTERVAL. Specification lists acceptable > values 0-4 all other values are reserved and bit 7 of DPCD 0x0000e > describes another feature. Currently the code uses all of DPCD 0x0000e and > can cause max wait for 1024 ms instead of 16 ms as specified table 2-158. > This address is read for both clock recovery and channel equalization. > > Signed-off-by: Matt Atwood <matthew.s.atwood@xxxxxxxxx> Tested-by: Benson Leung <bleung@xxxxxxxxxxxx> I tested this patch on that particularly problematic panel, with the out of spec value of 9. With the masking, the panel link trains successfully. Thanks! -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@xxxxxxxxxx Chromium OS Project bleung@xxxxxxxxxxxx
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