Hi,
Il 28/02/2018 17:34, Giulio Benetti ha scritto:
Hi,
Il 28/02/2018 16:55, Maxime Ripard ha scritto:
Hi,
On Wed, Feb 28, 2018 at 01:51:58PM +0100, Giulio Benetti wrote:
sun4i_dclk_round_rate is called before sun4i_tcon_mode_set,
so it finds dclk_min_div and dclk_max_div set to 0 and fails
adding crtc.
Move dclk_min_div and dclk_max_div to encoders init functions.
Signed-off-by: Giulio Benetti <giulio.benetti@xxxxxxxxxxxxxxxx>
I sent a similar patch there:
https://lists.freedesktop.org/archives/dri-devel/2018-February/166666.html
I've missed that.
And where you put it is better, since it's called every time set_mode is
called.
On lvds instead I don't see anything about this,
it should have the same potential problem.
Also I can't understand why it has been set min=7 and max=7 on lvds.
With those values I would obtain 77Mhz only.
And I can't find values on datasheet for minimum and maximum.
Submitted patchset for that.
I guess eventually, we'll want to remove the usage of the clock
framework entirely, but it's not really the scope of a fix.
Where would you handle dclk instead of tcon?
Don't mind.
--
Giulio Benetti
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Thanks
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