On Thu, Feb 15, 2018 at 12:32:58AM -0500, Daniele Castagna wrote:
> This patch adds YUV2YUV registers to enable and control per-plane
> RGB2RGB colos space conversion matrix.
>
> Change-Id: I8f421222da3587caea6373e2201e918f0c5e2646
Missing Signed-off-by, I think you can squash this into "drm/rockchip: Implement
drm plane->ctm property" as well.
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 7 +++
> drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 48 +++++++++++++++++++++
> 2 files changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> index aa8a5d2690376..fea5a087f4749 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> @@ -80,6 +80,13 @@ struct vop_misc {
> };
>
> struct vop_yuv2yuv {
> + struct vop_reg win0_r2r_en;
> + struct vop_reg win0_r2r_coefficients[12];
> + struct vop_reg win1_r2r_en;
> + struct vop_reg win1_r2r_coefficients[12];
> + struct vop_reg win2_r2r_en;
> + struct vop_reg win2_r2r_coefficients[12];
> +
> struct vop_reg win0_y2r_en;
> struct vop_reg win0_y2r_coefficients[12];
I'll revise my earlier feedback and propose:
#define NUM_CSC_COEFFICIENTS 12
#define NUM_R2R_WINDOWS 3
#define NUM_Y2R_WINDOWS 2
struct vop_csc_reg {
struct vop_reg en;
struct vop_reg coefficients[NUM_CSC_COEFFICIENTS];
};
struct vop_csc {
struct vop_csc_reg r2r[NUM_R2R_WINDOWS];
struct vop_csc_reg y2r[NUM_Y2R_WINDOWS];
};
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> index 0af95947f22d4..fb7b07aa4fa27 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> @@ -423,6 +423,54 @@ static const struct vop_output rk3399_output = {
> };
>
> static const struct vop_yuv2yuv rk3399_vop_yuv2yuv = {
> + .win0_r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
> + .win0_r2r_coefficients = {
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 0, 0xffff, 0),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 0, 0xffff, 16),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 4, 0xffff, 0),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 4, 0xffff, 16),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 8, 0xffff, 0),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 8, 0xffff, 16),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 12, 0xffff, 0),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 12, 0xffff, 16),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 16, 0xffff, 0),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 20, 0xffffffff, 0),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 24, 0xffffffff, 0),
> + VOP_REG(RK3399_WIN0_YUV2YUV_3X3 + 28, 0xffffffff, 0),
> + },
> +
> + .win1_r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
> + .win1_r2r_coefficients = {
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 0, 0xffff, 0),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 0, 0xffff, 16),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 4, 0xffff, 0),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 4, 0xffff, 16),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 8, 0xffff, 0),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 8, 0xffff, 16),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 12, 0xffff, 0),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 12, 0xffff, 16),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 16, 0xffff, 0),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 20, 0xffffffff, 0),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 24, 0xffffffff, 0),
> + VOP_REG(RK3399_WIN1_YUV2YUV_3X3 + 28, 0xffffffff, 0),
> + },
> +
> + .win2_r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 16),
> + .win2_r2r_coefficients = {
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 0, 0xffff, 0),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 0, 0xffff, 16),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 4, 0xffff, 0),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 4, 0xffff, 16),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 8, 0xffff, 0),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 8, 0xffff, 16),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 12, 0xffff, 0),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 12, 0xffff, 16),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 16, 0xffff, 0),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 20, 0xffffffff, 0),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 24, 0xffffffff, 0),
> + VOP_REG(RK3399_WIN2_YUV2YUV_3X3 + 28, 0xffffffff, 0),
> + },
> +
> .win0_y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
> .win0_y2r_coefficients = {
> VOP_REG(RK3399_WIN1_YUV2YUV_Y2R + 0, 0xffff, 0),
> --
> 2.16.1.291.g4437f3f132-goog
>
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--
Sean Paul, Software Engineer, Google / Chromium OS
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