tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-4.17-wip
head: 1d0e528594e2040c6c208be32bad4ad57437aabb
commit: 1d0e528594e2040c6c208be32bad4ad57437aabb [390/390] drm/amdgpu: used cached pcie gen info for SI
config: x86_64-randconfig-u0-02271135 (attached as .config)
compiler: gcc-5 (Debian 5.5.0-3) 5.4.1 20171010
reproduce:
git checkout 1d0e528594e2040c6c208be32bad4ad57437aabb
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/si.c: In function 'si_pcie_gen3_enable':
>> drivers/gpu/drm/amd/amdgpu/si.c:1500:34: error: 'CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2' undeclared (first use in this function)
if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
^
drivers/gpu/drm/amd/amdgpu/si.c:1500:34: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/amd/amdgpu/si.c:1501:6: error: 'CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3' undeclared (first use in this function)
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
^
drivers/gpu/drm/amd/amdgpu/si.c:1488:6: warning: unused variable 'ret' [-Wunused-variable]
int ret, i;
^
--
drivers/gpu/drm/amd/amdgpu/si_dpm.c: In function 'si_dpm_init':
drivers/gpu/drm/amd/amdgpu/si_dpm.c:7317:29: error: 'CAIL_PCIE_LINK_SPEED_SUPPORT_MASK' undeclared (first use in this function)
(adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
^
drivers/gpu/drm/amd/amdgpu/si_dpm.c:7317:29: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/amd/amdgpu/si_dpm.c:7318:3: error: 'CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT' undeclared (first use in this function)
CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
^
vim +/CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 +1500 drivers/gpu/drm/amd/amdgpu/si.c
1482
1483 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1484 {
1485 struct pci_dev *root = adev->pdev->bus->self;
1486 int bridge_pos, gpu_pos;
1487 u32 speed_cntl, current_data_rate;
1488 int ret, i;
1489 u16 tmp16;
1490
1491 if (pci_is_root_bus(adev->pdev->bus))
1492 return;
1493
1494 if (amdgpu_pcie_gen2 == 0)
1495 return;
1496
1497 if (adev->flags & AMD_IS_APU)
1498 return;
1499
> 1500 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
> 1501 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1502 return;
1503
1504 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1505 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1506 LC_CURRENT_DATA_RATE_SHIFT;
1507 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1508 if (current_data_rate == 2) {
1509 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1510 return;
1511 }
1512 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1513 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
1514 if (current_data_rate == 1) {
1515 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1516 return;
1517 }
1518 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1519 }
1520
1521 bridge_pos = pci_pcie_cap(root);
1522 if (!bridge_pos)
1523 return;
1524
1525 gpu_pos = pci_pcie_cap(adev->pdev);
1526 if (!gpu_pos)
1527 return;
1528
1529 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1530 if (current_data_rate != 2) {
1531 u16 bridge_cfg, gpu_cfg;
1532 u16 bridge_cfg2, gpu_cfg2;
1533 u32 max_lw, current_lw, tmp;
1534
1535 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1536 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1537
1538 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1539 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1540
1541 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1542 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1543
1544 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1545 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1546 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1547
1548 if (current_lw < max_lw) {
1549 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1550 if (tmp & LC_RENEGOTIATION_SUPPORT) {
1551 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1552 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1553 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
1554 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
1555 }
1556 }
1557
1558 for (i = 0; i < 10; i++) {
1559 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1560 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1561 break;
1562
1563 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1564 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1565
1566 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1567 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1568
1569 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1570 tmp |= LC_SET_QUIESCE;
1571 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1572
1573 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1574 tmp |= LC_REDO_EQ;
1575 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1576
1577 mdelay(100);
1578
1579 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1580 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1581 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1582 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1583
1584 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1585 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1586 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1587 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1588
1589 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1590 tmp16 &= ~((1 << 4) | (7 << 9));
1591 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1592 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1593
1594 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1595 tmp16 &= ~((1 << 4) | (7 << 9));
1596 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1597 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1598
1599 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1600 tmp &= ~LC_SET_QUIESCE;
1601 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1602 }
1603 }
1604 }
1605
1606 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1607 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1608 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1609
1610 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1611 tmp16 &= ~0xf;
1612 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1613 tmp16 |= 3;
1614 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1615 tmp16 |= 2;
1616 else
1617 tmp16 |= 1;
1618 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1619
1620 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1621 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
1622 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1623
1624 for (i = 0; i < adev->usec_timeout; i++) {
1625 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1626 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1627 break;
1628 udelay(1);
1629 }
1630 }
1631
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Attachment:
.config.gz
Description: application/gzip
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