From: Thierry Reding <treding@xxxxxxxxxx>
Rather than storing capabilities as flags in an integer, use a separate
boolean per capability. This simplifies the code that checks for these
capabilities.
Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
---
drivers/gpu/drm/bridge/tc358767.c | 6 +++---
drivers/gpu/drm/drm_dp_helper.c | 19 ++++++++++++++++---
drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++--
drivers/gpu/drm/tegra/sor.c | 4 ++--
include/drm/drm_dp_helper.h | 17 ++++++++++++++---
5 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 55037f999579..ad278a79feb3 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -635,8 +635,8 @@ static int tc_get_display_props(struct tc_data *tc)
tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
(tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
tc->link.base.lanes,
- (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
- "enhanced" : "non-enhanced");
+ (tc->link.base.caps.enhanced_framing) ? "enhanced" :
+ "non-enhanced");
dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
tc->link.assr, tc->assr);
@@ -1015,7 +1015,7 @@ static int tc_main_link_stream(struct tc_data *tc, int state)
if (state) {
value = VID_MN_GEN | DP_EN;
- if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
+ if (tc->link.base.caps.enhanced_framing)
value |= EF_EN;
tc_write(DP0CTL, value);
/*
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f401377a199d..6fbce4554029 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -315,6 +315,18 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
+static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps)
+{
+ caps->enhanced_framing = false;
+}
+
+void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
+ const struct drm_dp_link_caps *src)
+{
+ dest->enhanced_framing = src->enhanced_framing;
+}
+EXPORT_SYMBOL(drm_dp_link_caps_copy);
+
static void drm_dp_link_reset(struct drm_dp_link *link)
{
if (!link)
@@ -323,7 +335,8 @@ static void drm_dp_link_reset(struct drm_dp_link *link)
link->revision = 0;
link->max_rate = 0;
link->max_lanes = 0;
- link->capabilities = 0;
+
+ drm_dp_link_caps_reset(&link->caps);
link->rate = 0;
link->lanes = 0;
@@ -356,7 +369,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
if (values[2] & DP_ENHANCED_FRAME_CAP)
- link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
+ link->caps.enhanced_framing = true;
link->rate = link->max_rate;
link->lanes = link->max_lanes;
@@ -449,7 +462,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
values[0] = drm_dp_link_rate_to_bw_code(link->rate);
values[1] = link->lanes;
- if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
+ if (link->caps.enhanced_framing)
values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c
index 71192a0656e3..489fa81bb508 100644
--- a/drivers/gpu/drm/msm/edp/edp_ctrl.c
+++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c
@@ -447,7 +447,7 @@ static void edp_config_ctrl(struct edp_ctrl *ctrl)
data = EDP_CONFIGURATION_CTRL_LANES(ctrl->lane_cnt - 1);
- if (ctrl->dp_link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
+ if (ctrl->dp_link.caps.enhanced_framing)
data |= EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
depth = EDP_6BIT;
@@ -769,7 +769,7 @@ static int edp_do_link_train(struct edp_ctrl *ctrl)
*/
dp_link.lanes = ctrl->lane_cnt;
dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate);
- dp_link.capabilities = ctrl->dp_link.capabilities;
+ drm_dp_link_caps_copy(&dp_link.caps, &ctrl->dp_link.caps);
if (drm_dp_link_configure(ctrl->drm_aux, &dp_link) < 0)
return EDP_TRAIN_FAIL;
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index e3c3f5add411..f24c012f1b41 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -912,7 +912,7 @@ static int tegra_sor_compute_config(struct tegra_sor *sor,
num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
config->hblank_symbols = div_u64(num, pclk);
- if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
+ if (link->caps.enhanced_framing)
config->hblank_symbols -= 3;
config->hblank_symbols -= 12 / link->lanes;
@@ -2091,7 +2091,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
- if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
+ if (link.caps.enhanced_framing)
value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 216a388f467f..e3429abb03f9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1097,14 +1097,24 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
/*
* DisplayPort link
*/
-#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
+
+/**
+ * struct drm_dp_link_caps - DP link capabilities
+ * @enhanced_framing: enhanced framing capability (mandatory as of DP 1.2)
+ */
+struct drm_dp_link_caps {
+ bool enhanced_framing;
+};
+
+void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
+ const struct drm_dp_link_caps *src);
/**
* struct drm_dp_link - DP link capabilities and configuration
* @revision: DP specification revision supported on the link
* @max_rate: maximum clock rate supported on the link
* @max_lanes: maximum number of lanes supported on the link
- * @capabilities: bitmask of capabilities supported on the link
+ * @caps: capabilities supported on the link (see &drm_dp_link_caps)
* @rate: currently configured link rate
* @lanes: currently configured number of lanes
*/
@@ -1112,7 +1122,8 @@ struct drm_dp_link {
unsigned char revision;
unsigned int max_rate;
unsigned int max_lanes;
- unsigned long capabilities;
+
+ struct drm_dp_link_caps caps;
unsigned int rate;
unsigned int lanes;
--
2.15.1
_______________________________________________
dri-devel mailing list
dri-devel@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/dri-devel
