On 29/01/18 18:38, Boris Brezillon wrote: > Note that the TX byte clk should be configured to match the DPI pixel > clock, which means we should refuse any config where the variation is > too big to be recovered. Anyway, we still don't have a way to configure > the PLL rate (which is driving the TX byte clk), so there's not much I > can do about that right now. We could have the code to check the allowed difference in place. >> Another thing is that the mode->crtc_clock is in kHz, I wonder if that >> rounding can cause miscalculations in the above code. > > Do we really have modes exposing pixel clks not aligned on a Khz? I Well, I think the clocks in the logical video modes are aligned, but the actual clock from the display controller or the PHY most likely is not aligned. > know the display controller can adjust the timings, but then, the > variation caused by the Khz approx should not be that big (999Khz / > 10+MHz < 1/10000), and anyway, that's what the DRM framework > manipulates... Depends on how strict the HW is about the allowed difference between the crtc and the DSI IP. It maybe that that 1 Hz is one too many... But that can be avoided by just making sure that the check rounds the values properly, or maybe just reduces the allowed range by 1kHz on both ends. So I don't think it's an issue, but it is something to keep in mind. Tomi -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
