On Thu, Jan 25, 2018 at 7:55 AM, Philippe Cornu <philippe.cornu@xxxxxx> wrote: > The "adjusted_mode" clock value (ie the real pixel clock) is more > accurate than "mode" clock value (ie the panel/bridge requested > clock value). It offers a better preciseness for timing > computations and allows to reduce the extra dsi bandwidth in > burst mode (from ~20% to ~10-12%, hw platform dependant). > > Signed-off-by: Philippe Cornu <philippe.cornu@xxxxxx> > --- > Note: This patch replaces "drm/bridge/synopsys: dsi: add optional pixel clock" These two appear to be the same for my cases, but at least nothing breaks: Tested-by: Brian Norris <briannorris@xxxxxxxxxxxx> _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
