On 01/16/2018 12:06 AM, Lyude Paul wrote:
It's here! After a lot of investigation, rewrites, and traces, I present
the patch series to implement all known levels of clockgating for
Kepler1 and Kepler2 GPUs.
Starting with Fermi GPUs (this is probably present on earlier GPUs as
well, but with a far less easy to manage interface), nvidia added two
clockgating levels that are handled mostly in firmware (with the
exception of course, of the driver initially programming all of the
register values containing engine delays and that stuff):
- CG_CTRL - Main register for enabling/disabling clockgating for
engines and hw blocks
- BLCG - "Block-level clockgating", a deeper level of clockgating
Starting with kepler2 as well, nvidia also introduced:
- SLCG - "??? clockgating" even deeper level of clockgating
FWIW, SLCG stands for "second level clock gating".
Cheers,
Mikko
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